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参数资料
| 型号： | FAN5365UC03X |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.84 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, PBGA9 |
| 封装： | 1.27 X 1.29 MM, 0.40 MM PITCH, WLCSP-9 |
| 文件页数： | 14/24页 |
| 文件大小： | 1014K |
| 代理商： | FAN5365UC03X |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5365 Rev. 1.0.4
21
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High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) modes are identical, except the bus speed
for HS mode is 3.4MHz. HS mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in Fast or Fast Plus mode
(less than 1MHz clock) and slaves do not acknowledge
(ACK) this transmission.
The master then generates a repeated start condition
(Figure 42) that causes all slaves on the bus to switch to HS
mode. The master then sends I
2C packets, as described
above, using the HS mode clock rate and timing.
The bus remains in HS mode until a stop bit (Figure 41) is
sent by the master. While in HS mode, packets are
separated by repeated start conditions.
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as
Master Drives Bus
and
Slave Drives Bus
.
All addresses and data are MSB first.
Table 8. I
2C Bit Definitions for Figure 43 and Figure 44
Symbol
Definition
S
START, Figure 40.
A
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
R
Repeated START, see Figure 42.
P
STOP, see Figure 41.
S
Slave Address
A
Reg Addr
A
P
0
7 bits
8 bits
Data
000
Figure 43. Write Transaction
S
Slave Address
A
Reg Addr
A
0
7 bits
8 bits
R
Slave Address
7 bits
1
A
Data
A
8 bits
00
0
1
P
Figure 44. Read Transaction
Register Descriptions
Default Values
Each option of the FAN5365 (see Table 9) has different
default values for the some of the register bits. Table 9 defines
both the default values and the bit’s type (as defined in Table
10) for each available option.
Table 9. Default Values and Bit Types for VSEL and CONTROL Registers
VSEL0
Option
7
6
5
4
3
2
1
0
VOUT
00
1
0
1
0
1.05
02
1
0
1
0
0.95
03
1
0
1
0
1
0
1.00
06
1
0
1
1.80
VSEL1
Option
7
6
5
4
3
2
1
0
VOUT
00
1
0
1
0
1.20
02
1
0
1
0
1.10
03
1
0
1
0
1.20
06
1
0
1
1.80
CONTROL1
Option
7
6
5
4
3
2
1
0
00, 02
1
0
1
0
03, 06
1
0
1
0
CONTROL2
Option
7
6
5
4
3
2
1
0
00, 02
0
1
0
1
03, 06
0
1
Table 10. Bit Type Definitions for Table 9
#
Active Bit
Changing this bit changes the behavior of the converter, as described below.
#
Disabled
Converter logic ignores changes made to this bit. Bit can be written and read-back.
#
Read-Only
Writing to this bit through I
2C does not change the read-back value, nor does it change converter behavior.
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