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参数资料
| 型号： | FAN5365UC03X |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.84 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, PBGA9 |
| 封装： | 1.27 X 1.29 MM, 0.40 MM PITCH, WLCSP-9 |
| 文件页数： | 15/24页 |
| 文件大小： | 1014K |
| 代理商： | FAN5365UC03X |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5365 Rev. 1.0.4
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Bit Definitions
Table 11 defines the operation of each register bit.
Superscript characters define the default state for each
option. Superscripts
0,2,3,6 signify the default values for
options 00, 02, 03, and 06, respectively.
A signifies the
default for all options.
Table 11. Bit Definitions
Bit
Name
Value
Description
VSEL0
Register Address: 00
7
EN_DCDC
0
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write
to bit 7 in either register establishes the EN_DCDC value.
1
A
Device enabled when EN pin is HIGH, disabled when EN is LOW.
6
Reserved
1
A
5:0
DAC[5:0]
Table 9
A
6-bit DAC value to set VOUT.
VSEL1
Register Address: 01
7
EN_DCDC
0
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write
to bit 7 in either register establishes the EN_DCDC value.
1
A
Device enabled when EN pin is HIGH, disabled when EN is LOW.
6
Reserved
1
A
5:0
DAC[5:0]
Table 9
A
6-bit DAC value to set VOUT.
CONTROL1
Register Address: 02
7:6
Reserved
10
A
Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be
used to distinguish between vendors via I
2C.
5
Reserved
1
A
4
HW_nSW
0
VOUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting
the GO bit.
1
A
VOUT is programmed by the VSEL pin. VOUT = VSEL1 when VSEL is HIGH and VOUT = VSEL0
when VSEL is LOW.
3:2 MODE_CTRL
00
A
Operation follows MODE0, MODE1.
01
PFM with automatic transitions to PWM, regardless of VSEL.
10
PFM disabled (forced PWM), regardless of VSEL.
11
PFM with automatic transitions to PWM, regardless of VSEL.
1
MODE1
0
A
PFM disabled (forced PWM) when regulator output is controlled by VSEL1.
1
PFM with automatic transitions to PWM when regulator output is controlled by VSEL1.
0
MODE0
0
A
PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on
the operation of the regulator.
1
CONTROL2
Register Address: 03
7
GO
0
A
This bit has no effect when HW_nSW = 1. At the end of a VOUT transition, this bit is reset to 0.
1
Starts a VOUT transition if HW_nSW = 0.
6
OUTPUT_
DISCHARGE
0
3,6
When the regulator is disabled, VOUT is not discharged.
1
0,2
When the regulator is disabled, VOUT discharges through an internal pull-down.
5
PWROK
(read only)
0
VOUT is not in regulation or is in current limit.
1
VOUT is in regulation.
4:3
Reserved
00
A
2:0
DEFSLEW
000
VOUT slews at 0.15mV/μs during positive VOUT transitions.
001
VOUT slews at 0.30mV/μs during positive VOUT transitions.
010
VOUT slews at 0.60mV/μs during positive VOUT transitions.
011
VOUT slews at 1.20mV/μs during positive VOUT transitions.
100
VOUT slews at 2.40mV/μs during positive VOUT transitions.
101
VOUT slews at 4.80mV/μs during positive VOUT transitions.
110
VOUT slews at 9.60mV/μs during positive VOUT transitions.
111
A
Positive VOUT transitions use single-step mode (see Figure 37).
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