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参数资料
| 型号： | FAN8060EMPX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1A 10MLP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 5.5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.21MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-MLP |
| 其它名称： | FAN8060EMPXDKR |
Applications Information
Refer to Figure 1 for reference designators.
Output Voltage Setting
The output voltage of the FAN8060 can be set from
1.2 V to V IN by an external resistor divider, given by the
following equation:
Input Capacitor Selection
The input capacitor reduces the RMS current drawn
from the input and switching noise from the device. The
combined RMS current rating for the input capacitor
should be greater than the value calculated by the
following equation:
V OUT = 1 . 2 ( 1 +
R 2
R 3
)
(2)
I RMS = I OUTMAX ? ( D ? D 2 )
(5)
where, V OUT equals the output voltage.
where:
I RMS
= RMS current of the input capacitor; and
Inductor Selection
Typically, the inductor value is chosen based on ripple
current ( ? I L ), which is chosen between 10% and 35% of
the maximum DC load. Regulator designs that require
fast transient response use a higher ripple-current
setting, while regulator designs that require higher
efficiency keep ripple current on the low side and
operate at a lower switching frequency.
For a given output voltage ripple requirement, L can be
calculated by the following equation:
I OUTMAX = Maximum output current.
Small, high value, inexpensive, lower-ESR ceramic
capacitors are recommended; 10 μF ceramic
capacitors with X7R or X5R should be adequate for
1 A applications.
Loop Compensation
The loop is compensated using a feedback network
shows a Type-2 compensation network used to
L ≥
V OUT ? (1 ? D )
? I L ? f S
(3)
stabilize the FAN8060.
V out
where;
D = Duty ratio (V O /V IN );
f S = Switching frequency; and
? I L = Inductor ripple value, typically set to 10% -
35% of the maximum steady-state load current.
R2
R3
V FB
-
+
G m
R C
V e
C A
The inductor should have a low DCR to minimize the
conduction losses and maximize efficiency. Some
V ref
C C
Table 1. Recommended Inductors (3.3 μH)
Figure 14. Compensation Network
Size[mm2]
7x7x3
5x5x2
4x4x2
2.6x2.8x1.2
DCR
23 m ?
60 m ?
78 m ?
130 m ?
Part Number
SLF7032T-3R3
LTF5022T-3R3
VLCF4020T-3R3
VLF3012AT-3R3
Vendor
TDK
TDK
TDK
TDK
The goal of the compensation design is to shape the
frequency response of the converter to achieve high
DC gain and fast transient, while maintaining loop
stability. FAN8060 employs peak-current-mode control
for easy use and fast transient response. Current mode
control helps simplify the loop to a one-pole and one
zero system.
The DC gain of the voltage feedback loop is given by:
Output Capacitor Selection
The output capacitor is selected based on the needs of
the final application and its output ripple requirements.
A VDC = R L ? G CS ? A VEA ?
V FB
V OUT
(6)
A larger output capacitor value reduces the output
ripple voltage. The formula of output ripple Δ V OUT is:
where:
A VDC = DC gain of the feedback loop;
? V OUT ? ? I L ? ? ESR +
?
?
?
?
1
8 ? C OUT ? f S
?
?
(4)
R L = Load resistor value (V OUT /I OUT );
G CS = Current sense gain (3 A/V);
where C OUT is the output capacitor.
A VEA = Error amplifier voltage gain (550 V/V); and
ESR is the equivalent series resistance of the output
capacitor.
V FB
= Feedback threshold voltage (1.2 V).
? 2013 Fairchild Semiconductor Corporation
FAN8060 ? Rev. 1.0.1
9
www.fairchildsemi.com
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