参数资料
型号: FDD86102
厂商: Fairchild Semiconductor
文件页数: 2/6页
文件大小: 0K
描述: MOSFET N-CH 100V 8A DPAK
产品目录绘图: DPAK, TO-252(AA)
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 100V
电流 - 连续漏极(Id) @ 25° C: 8A
开态Rds(最大)@ Id, Vgs @ 25° C: 24 毫欧 @ 8A,10V
Id 时的 Vgs(th)(最大): 4V @ 250µA
闸电荷(Qg) @ Vgs: 19nC @ 10V
输入电容 (Ciss) @ Vds: 1035pF @ 50V
功率 - 最大: 3.1W
安装类型: 表面贴装
封装/外壳: TO-252-3,DPak(2 引线+接片),SC-63
供应商设备封装: D-Pak
包装: 标准包装
产品目录页面: 1606 (CN2011-ZH PDF)
其它名称: FDD86102DKR
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 80 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
100
67
1
±100
V
mV/°C
μ A
nA
On Characteristics (Note 2)
V GS(th)
Δ V GS(th )
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
2
3.1
-8.5
4
V
mV/°C
V GS = 10 V, I D = 8 A
19
24
r DS(on)
Static Drain to Source On Resistance
V GS = 6 V, I D = 6 A
26
38
m Ω
V GS = 10 V, I D = 8 A, T J = 125 °C
33
44
g FS
Forward Transconductance
V DS = 10 V, I D = 8 A
21
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 50 V, V GS = 0 V,
f = 1 MHz
780
180
15
0.4
1035
240
25
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
7.6
15
ns
t r
t d(off)
t f
Q g
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
V DD = 50 V, I D = 8 A,
V GS = 10 V, R GEN = 6 Ω
V GS = 0 V to 10 V
3
13.4
2.9
13.4
10
24
10
19
ns
ns
ns
nC
Q g
Q gs
Total Gate Charge
Gate to Source Gate Charge
V GS = 0 V to 5 V
V DD = 50 V,
I D = 8 A
7.6
4.0
11
nC
nC
Q gd
Gate to Drain “Miller” Charge
3.7
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = 8 A
V GS = 0 V, I S = 2.6 A
I F = 8 A, di/dt = 100 A/ μ s
(Note 2)
(Note 2)
0.8
0.7
43
43
1.3
1.2
68
68
V
ns
nC
Notes :
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
a. 40 °C/W when mounted on a
1 in 2 pad of 2 oz copper.
b. 96 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3. E AS 121 mJ is based on starting T J = 25 ° C, L = 3 mH, I AS = 9 A, V DD = 100 V, V GS = 10 V. 100% test at L = 0.1 mH, I AS = 30 A.
4. Pulsed Drain current is tested at 300 μ s with 2% duty cycle. For repetitive pulses, the pulse width is limited by the maximum junction temperature.
?2012 Fairchild Semiconductor Corporation
FDD86102 Rev.C7
2
www.fairchildsemi.com
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