参数资料
型号: FDMF6705
厂商: Fairchild Semiconductor
文件页数: 4/19页
文件大小: 0K
描述: MODULE DRMOS HI PERF HF POWER66
标准包装: 3,000
系列: XS™ DrMOS
类型: 高端/低端驱动器
输入类型: PWM
输出数: 1
电流 - 峰值输出: 40A
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 40-PowerTFQFN
供应商设备封装: 40-PQFN(6x6)
包装: 带卷 (TR)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCIN, VDRV, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins
VIN to PGND, CGND Pins
BOOT, GH to VSWH, PHASE Pins
BOOT, PHASE, GH to CGND Pins
VSWH to CGND/PGND (DC Only)
VSWH to PGND (<20 ns)
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-8.0
Max.
6.0
30.0
6.0
30.0
30.0
33.0
Unit
V
BOOT to VDRV
BOOT to VDRV (<20 ns)
22.0
25.0
I THWN#
I O(AV)(1)
θ JPCB
T A
T J
T STG
THWN# Sink Current
V IN =19 V, V O =1.0 V
Junction-to-PCB Thermal Resistance
Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
f SW =300 kHz
f SW =1 MHz
-0.1
-40
-55
7.0
38
35
3.5
+125
+150
+150
mA
A
°C/W
°C
°C
°C
ESD
Electrostatic Discharge Protection
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
2000
1000
V
Note:
1. I O(AV) is rated using Fairchild’s DrMOS evaluation board, T A = 25°C, natural convection cooling. This rating is limited
by the peak DrMOS temperature, T J = 150°C, and varies depending on operating conditions and PCB layout. This
rating can be changed with different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
24.0
Symbol
V CIN
V DRV
V IN
Parameter
Control Circuit Supply Voltage
Gate Drive Circuit Supply Voltage
Output Stage Supply Voltage
Min.
4.5
4.5
3.0
Typ.
5.0
5.0
12.0
Max.
5.5
5.5
(2)
Unit
V
V
V
Note:
2.
Operating at high V IN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application
Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.
? 2011 Fairchild Semiconductor Corporation
FDMF6705 ? Rev. 1.0.4
4
www.fairchildsemi.com
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