参数资料
| 型号： | FDMF6823C |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | MODULE DRMOS 50A 40-PQFN |
| 标准包装： | 3,000 |
| 系列： | XS™ DrMOS |
| 类型： | 高端/低端驱动器 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 电流 - 输出 / 通道： | 50A |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-PowerTFQFN |
| 供应商设备封装： | 40-PQFN（6x6） |
| 包装： | 带卷 (TR) |
PCB Layout Guidelines
MOSFETs are used in the output
4. PowerTrench
Figure 31 and Figure 32 provide an example of a proper
layout for the FDMF6823C and critical components. All
of the high-current paths, such as VIN, VSWH, VOUT,
and GND copper, should be short and wide for low
inductance and resistance. This aids in achieving a
more stable and evenly distributed current flow, along
with enhanced heat radiation and system performance.
Recommendations for PCB Designers
1. Input ceramic bypass capacitors must be placed
close to the VIN and PGND pins. This helps reduce
the high-current power loop inductance and the input
current ripple induced by the power MOSFET
switching operation.
2. The V SWH copper trace serves two purposes. In
addition to being the high-frequency current path
from the DrMOS package to the output inductor, it
serves as a heat sink for the low-side MOSFET in
the DrMOS package. The trace should be short and
wide enough to present a low-impedance path for
the high-frequency, high-current flow between the
DrMOS and inductor. The short and wide trace
minimizes electrical losses as well as the DrMOS
temperature rise. Note that the V SWH node is a high-
voltage and high-frequency switching node with high
noise potential. Care should be taken to minimize
coupling to adjacent traces. Since this copper trace
acts as a heat sink for the lower MOSFET, balance
using the largest area possible to improve DrMOS
cooling while maintaining acceptable noise emission.
3. An output inductor should be located close to the
FDMF6823C to minimize the power loss due to the
V SWH copper trace. Care should also be taken so the
inductor dissipation does not heat the DrMOS.
?
stage and are effective at minimizing ringing due to
fast switching. In most cases, no VSWH snubber is
required. If a snubber is used, it should be placed
close to the VSWH and PGND pins. The selected
resistor and capacitor need to be the proper size for
power dissipation.
5. VCIN, VDRV, and BOOT capacitors should be
placed as close as possible to the VCIN-to-CGND,
VDRV-to-CGND, and BOOT-to-PHASE pin pairs to
ensure clean and stable power. Routing width and
length should be considered as well.
6. Include a trace from the PHASE pin to the VSWH pin
to improve noise margin. Keep this trace as short as
possible.
7. The layout should include the option to insert a
small-value series boot resistor between the boot
capacitor and BOOT pin. The boot-loop size,
including R BOOT and C BOOT , should be as small as
possible. The boot resistor may be required when
operating above 15 V IN and is effective at controlling
the high-side MOSFET turn-on slew rate and V SHW
overshoot. R BOOT can improve noise operating
margin in synchronous buck designs that may have
? 2011 Fairchild Semiconductor Corporation
FDMF6823C ? Rev. 1.0.3
noise issues due to ground bounce or high positive
and negative V SWH ringing. Inserting a boot
resistance lowers the DrMOS efficiency. Efficiency
versus noise trade-offs must be considered. R BOOT
values from 0.5 Ω to 3.0 Ω are typically effective in
reducing V SWH overshoot.
8. The VIN and PGND pins handle large current
transients with frequency components greater than
100 MHz. If possible, these pins should be
connected directly to the VIN and board GND
planes. The use of thermal relief traces in series with
these pins is discouraged since this adds inductance
to the power path. This added inductance in series
with either the VIN or PGND pin degrades system
noise immunity by increasing positive and negative
V SWH ringing.
9. GND pad and PGND pins should be connected to
the GND copper plane with multiple vias for stable
grounding. Poor grounding can create a noise
transient offset voltage level between CGND and
PGND. This could lead to faulty operation of the gate
driver and MOSFETs.
10. Ringing at the BOOT pin is most effectively
controlled by close placement of the boot capacitor.
Do not add an additional BOOT to the PGND
capacitor. This may lead to excess current flow
through the BOOT diode.
11. The SMOD# and DISB# pins have weak internal
pull-up and pull-down current sources, respectively.
These pins should not have any noise filter
capacitors. Do not to float these pins unless
absolutely necessary.
12. Use multiple vias on the VIN and VOUT copper
areas to interconnect top, inner, and bottom layers
to distribute current flow and heat conduction. Do
not put many vias on the VSWH copper to avoid
extra parasitic inductance and noise on the
switching waveform. As long as efficiency and
thermal performance are acceptable, place only
one VSWH copper on the top layer and use no vias
on the VSWH copper to minimize switch node
parasitic noise. Vias should be relatively large and
of reasonably low inductance. Critical high-
frequency components, such as R BOOT , C BOOT , RC
snubber, and bypass capacitors; should be located
as close to the respective DrMOS module pins as
possible on the top layer of the PCB. If this is not
feasible, they can be connected from the backside
through a network of low-inductance vias.
www.fairchildsemi.com
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