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| 型号： | FDMS7672 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 30V 19A POWER56 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Power 56 Pkg/Design Change 14/Apr/2009 |
| 产品目录绘图： | Power56 Single |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 30V |
| 电流 - 连续漏极(Id) @ 25° C： | 19A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 5 毫欧 @ 19A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 44nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 2960pF @ 15V |
| 功率 - 最大： | 2.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-PQFN，Power56 |
| 供应商设备封装： | Power56 |
| 包装： | 标准包装 |
| 产品目录页面： | 1609 (CN2011-ZH PDF) |
| 其它名称： | FDMS7672DKR |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DS S
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current, Forward
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 24 V, V GS = 0 V
V GS = 20 V, V DS = 0 V
30
15
1
100
V
mV / °C
μ A
nA
On Characteristics
V GS(th)
? V GS(th )
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
1.25
2.0
-7
3.0
V
mV/°C
V GS = 10 V, I D = 19 A
3.6
5.0
r DS(on)
Static Drain to Source On Resistance
V GS = 4.5 V, I D = 15 A
5.2
6.9
m ?
V GS = 10 V, I D = 19 A, T J = 125 °C
4.9
6.8
g FS
Forward Transconductance
V DS = 5 V, I D = 19 A
64
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 15 V, V GS = 0 V,
f = 1 MHz
2225
685
90
0.7
2960
910
130
1.5
pF
pF
pF
?
Switching Characteristics
t d(on)
Turn-On Delay Time
13
23
ns
t r
t d(off)
t f
Q g
Q g
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V DD = 15 V, I D = 19 A,
V GS = 10 V, R GEN = 6 ?
V GS = 0 V to 10 V
V GS = 0 V to 4.5 V V DD = 15 V,
I D = 19 A
5
25
4
31
14
7.6
3.7
10
40
10
44
19
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = 2.1 A
V GS = 0 V, I S = 19 A
(Note 2)
(Note 2)
0.7
0.8
32
14
0.95
1. 1
51
24
V
ns
nC
t a
t b
S
Reverse Recovery Fall Time
Reverse Recovery Rise Time
Softness (t b /t a )
I F = 19 A, di/dt = 100 A/ μ s
15
17
1.1
nC
nC
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = 19 A, di/dt = 300 A/ μ s
26
25
42
40
ns
nC
Notes :
1. R θ JA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a. 50 °C/W when mounted on a
1 in 2 pad of 2 oz copper.
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 30 0 μ s, Duty cycle < 2.0%.
3. E AS of 72 mJ is based on starting T J = 25 ° C, L = 1 mH, I AS = 12 A, V DD = 27 V, V GS = 10 V. 100% test at L = 0.3 mH, I AS = 17 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
FDMS7672 Rev . D
2
www.fairchildsemi.com
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