参数资料
型号: FDMS7700S
厂商: Fairchild Semiconductor
文件页数: 2/12页
文件大小: 0K
描述: MOSFET 2N-CH 30V POWER56
产品目录绘图: 8-MLP, Power33, 56 Dual
标准包装: 1
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 30A,40A
开态Rds(最大)@ Id, Vgs @ 25° C: 7.5 毫欧 @ 12A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 28nC @ 10V
输入电容 (Ciss) @ Vds: 1750pF @ 15V
功率 - 最大: 1W
安装类型: 表面贴装
封装/外壳: Power56
供应商设备封装: Power56
包装: 标准包装
产品目录页面: 1609 (CN2011-ZH PDF)
其它名称: FDMS7700SDKR
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DS S
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 1 mA, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
I D = 1 mA, referenced to 25 °C
V DS = 24 V, V GS = 0 V
V GS = 20 V, V DS = 0 V
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
30
30
15
14
1
500
100
100
V
mV /° C
μ A
μ A
nA
nA
On Characteristics
V GS(th)
? V GS(th )
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
V GS = V DS , I D = 1 mA
I D = 250 μ A, referenced to 25 °C
I D = 1 mA, referenced to 25 °C
Q1
Q2
Q1
Q2
1
1
1.8
1.5
-6
-4
3
3
V
mV/°C
V GS = 10 V, I D = 12 A
6.0
7.5
V GS = 4.5 V, I D = 10 A
Q1
8.5
12
r DS(on)
Drain to Source On Resistance
V GS = 10 V, I D = 12 A , T J = 125 °C
V GS = 10 V, I D = 20 A
V GS = 4.5 V, I D = 18 A
Q2
8.3
1.9
2.2
12
2.4
2.9
m ?
V GS = 10 V, I D = 20 A , T J = 125 °C
2.1
3.4
g FS
Forward Transconductance
V DS = 5 V, I D = 12 A
V DS = 5 V, I D = 20 A
Q1
Q2
63
160
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q1:
V DS = 15 V, V GS = 0 V, f = 1 MHZ
Q2:
V DS = 15 V, V GS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1315
7240
445
2690
45
185
0.9
0.8
1750
9630
600
3580
70
280
pF
pF
pF
?
Switching Characteristics
t d(on)
Turn-On Delay Time
Q1
Q2
8.6
21
18
34
ns
t r
t d(off)
t f
Q g
Q g
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1:
V DD = 15 V, I D = 12 A, R GEN = 6 ?
Q2:
V DD = 15 V, I D = 20 A, R GEN = 6 ?
V GS = 0 V to 10 V Q1
V DD = 15 V,
V GS = 0 V to 4.5 V I D = 12 A
Q2
V DD = 15 V,
I D = 20 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
2.5
9.2
20
58
2.3
6.8
20
105
9.3
48
4.3
19
2.2
11
10
18
32
93
10
14
28
147
13
67
ns
ns
ns
nC
nC
nC
nC
?2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C
www.fairchildsemi.com
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