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参数资料
| 型号： | FDS8449_F085 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 40V 7.6A 8-SOIC |
| 标准包装： | 2,500 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 40V |
| 电流 - 连续漏极(Id) @ 25° C： | 7.6A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 29 毫欧 @ 7.6A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 11nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 760pF @ 20V |
| 功率 - 最大： | 1W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Drain-Source Avalanche Ratings
(Note 3)
E AS
I AS
Drain-Source Avalanche Energy
Drain-Source Avalanche Current
V DD = 40 V,
I D = 7.3 A, L = 1 mH
7.3
27
mJ
A
Off Characteristics
BV DSS
Drain–Source Breakdown Voltage
V GS = 0 V,
I D = 250 μ A
40
V
Δ BV DSS
Δ T J
Breakdown Voltage Temperature
Coefficient
I D = 250 μ A, Referenced to 25 ° C
34
mV/ ° C
I DSS
I GSS
Zero Gate Voltage Drain Current
Gate–Body Leakage
V DS = 32 V,
V GS = ± 20 V,
V GS = 0 V
V DS = 0 V
1
± 100
μ A
nA
On Characteristics
(Note 2)
V GS(th)
Δ V GS(th)
Δ T J
R DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
V DS = V GS , I D = 250 μ A
I D = 250 μ A, Referenced to 25 ° C
V GS = 10 V, I D = 7.6 A
1
1.9
–5
21
3
29
V
mV/ ° C
m Ω
On–Resistance
V GS = 4.5 V, I D = 6.8 A
V GS = 10 V, I D = 7.6 A, T J =125 ° C
26
29
36
43
g FS
Forward Transconductance
V DS = 10 V,
I D = 7.6 A
21
S
Dynamic Characteristics
C iss
C oss
C rss
R G
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 20 V,
f = 1.0 MHz
f = 1.0 MHz
V GS = 0 V,
760
100
60
1.2
pF
pF
pF
Ω
Switching Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
V DD = 20 V,
V GS = 10 V,
V DS = 20 V,
V GS = 5 V
I D = 1 A,
R GEN = 6 Ω
I D = 7.6 A,
9
5
23
3
7.7
2.4
18
10
17
6
11
ns
ns
ns
ns
nC
nC
Q gd
Gate–Drain Charge
2.8
nC
Drain–Source Diode Characteristics
V SD
Drain–Source Diode Forward
Voltage
V GS = 0 V,
I S = 2.1 A
(Note 2)
0.76
1.2
V
t rr
Q rr
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
I F = 7.6 A,
d iF /d t = 100 A/μs
17
7
nS
nC
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
a)
50°C/W when mounted
on a 1in 2 pad of 2 oz
b) 125°C/W when mounted on a
minimum pad.
copper
Scale 1 : 1 on letter size paper
2 Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
3. BV(avalanche) Single-Pulse rating is guaranteed if device is operated within the UIS SOA boundary of the device.
FDS8449 _F085 Rev . A
2
www.fairchildsemi.com
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