参数资料
型号: FIN324CMLX
厂商: Fairchild Semiconductor
文件页数: 16/19页
文件大小: 0K
描述: IC SER DES 24BIT ULP 40-MLP
产品变化通告: Design/Process Change 07/May/2007
标准包装: 1
系列: *
其它名称: FIN324CMLXDKR
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.1.4
6
SerDes
FIN324C
24-Bit
Ultra-Low
Power
Serializer
/
Deserializer
Supporting
Single
and
Dual
Displays
Serial I/O Signals
CTL I/O Technology
The serial I/O is implemented using Fairchild’s
proprietary differential CTL I/O technology. During data
transfers, the serial I/O are powered up to a normal
operating mode around .5V. Upon completion of a data
transfer, the serial I/O goes to a lower power mode
around VDDS.
Serial I/O Orientation Logic
The serial I/O signal traces should not cross between
the master and the slave. The pin locations have been
designed to eliminate the need to cross traces. See
Table 7, Figure 4, and Figure 5.
Table 7. Serial Pin Orientation
Master (M/S=1) (Pad/Pin #)
Slave (M/S=0) (Pad/Pin #)
Package
CKS+
CKS-
DS-
DS+
CKS+
CKS-
DS-
DS+
MLP
2
3
6
7
6
3
2
BGA
D1
E1
F1
G1
F1
E1
D1
BGA
Slave
A
B
C
D
E
F
G
1
2
3
456
<DS+>
<DS->
<CKS->
<CKS+>
BGA
Master
G
F
E
D
C
B
A
DS-
CKS-
CKS+
65
4
3
2
1
DS+
21
22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
2
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
MLP
Master
M/S
PAR/SPI
/RES
DS+
DS-
VDDA
VDDS
CKS-
CKS+
CKSEL(H)
MLP
Slave
CKSEL(H)
(DS+)
(DS-)
VDDS
VDDA
(CKS-)
(CKS+)
/RES
PAR/SPI
M/S
Figure 4.
BGA Pair
Figure 5.
MLP Pair
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