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参数资料
| 型号： | FIN324CMLX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 5/19页 |
| 文件大小： | 0K |
| 描述： | IC SER DES 24BIT ULP 40-MLP |
| 产品变化通告： | Design/Process Change 07/May/2007 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | FIN324CMLXDKR |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.1.4
13
SerDes
FIN324C
—
24-Bit
Ultra-Low
Power
Serializer
/
Deserializer
Supporting
Single
and
Dual
Displays
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
AC Deserializer Specifications
tR0, tF0
Output Edge Rates of
WCLK0,WCLK1
SLEW=0, CL=5pF 20% to 80%
(5)
8
17
ns
SLEW=1, CL=5pF 20% to 80%
(5)
10
tR1, tF1
Output Edge Rates of R/W,
DP[17:0] CNTL[5:0]
SLEW=0, CL=5pF 20% to 80%
(5)
8
22
ns
SLEW=1, CL=5pF 20% to 80%
(5)
17
tCS
CNTL[5:0],R/W to Falling
Edge of WCLKn
M/S=0
(5), CL=5pF 50% to 50%(5)
Figure 15
0
4
ns
tPDV-WR0 DP, CNTL to WCLK0 ↑
PAR/SPI=1
(5), Figure 15
50
60
ns
tPDV-WR1 DP, CNTL to WCLK1 ↑
PAR/SPI=1
(5), Figure 15
18
24
ns
tPDV-RD
CNTL to WCLKn ↑
PAR/SPI=1
(5), Figure 17
200
224
ns
tPDV-SPI
Data, CNTL to SCLK ↑
PAR/SPI=0
(5), Figure 16
40
60
ns
tPWL-WR0
WCLK0 Pulse Width Low;
Write Mode
M/S=0, R/W=0, PAR/SPI=1
(5,7)
Figure 15
50
56
ns
tPWL-WR1
WCLK1 Pulse Width Low;
Write Mode
M/S=0, R/W=0, PAR/SPI=1
(5,7)
Figure 15
18
20
ns
tPWL-RD
Pulse Width Low of WCLK;
Read Mode
M/S=0, R/W=1, PAR/SPI=1
(5,7)
Figure 17
200
220
ns
tPWL-SPI
Pulse Width Low of WCLK;
SPI Mode
M/S=0, R/W=0, PAR/SPI=0
(5,7)
Figure 16
40
56
ns
AC Data Latencies
tPD-WR0
Write Latency
WRITE Mode, CKSEL=0
(8,9,10)
Figure 15
147
ns
tPD-WR1
Write Latency
WRITE Mode, CKSEL=1
(8,9,10)
Figure 15
111
ns
tPD-RD
Total Read Latency
READ Mode
(8,10,11)
Figure 17
340
480
ns
tPD-RDC
Read Control Latency
READ Mode
(8,10,12)
Figure 17
276
ns
tPD-RDD
Read Data Latency
READ Mode
(8,10,13)
Figure 17
84
ns
tPD-SPI
SPI Write Latency
SPI-WRITE Mode
(8,10,14)
Figure 16
115
ns
AC Oscillator Specifications
fOSC
Serial Operating Frequency
240
275
310
MHz
tOSC-STBY
Oscillator Stabilization Time
After Standby
VDDA=VDDS=2.75V
/RES=1, /STBY
↑ Transition
15
30
s
tOSC-RES
Oscillator Stabilization Time
After Reset
VDDA=VDDS=2.75V
/STBY=1, /RES
↑ Transition
30
50
s
AC Reset and Standby Timing
tVDD-OFF
Power Down Relative to
/RES
(15)
Figure 19
20
s
tSTRB-RES /RES after last STRBn
↑
M/S=1, /STBY=1, R/W=0
(16)
Figure 19
0
ns
tSTRB-STBY
Standby time after last
strobe
M/S=1, /STBY=1
(17)
Figure 19
200
ns
tRES-OFF
Master/Slave Reset Disable
Time
M/S=1 /STBY=1, /RES=
↓
Figure 19
15
20
s
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