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参数资料
| 型号： | FM33256-G |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO14 |
| 封装： | GREEN, MS-012AB, SOIC-14 |
| 文件页数： | 18/28页 |
| 文件大小： | 320K |
| 代理商： | FM33256-G |
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FM33256/FM3316 SPI Companion w/ FRAM
Rev. 2.0
Feb. 2009
Page 25 of 28
3
tDOG1 is the programmed StartTime and tDOG2 is the programmed EndTime in registers 0Bh and 0Ch, VDD > VTP, and tRPU
satisfied. The StartTime has a resolution of 25ms. The EndTime has a resolution of 60ms.
4
The /RST pin will drive low for this amount of time after the internal reset circuit is activated due to a watchdog, low
voltage, or manual reset event.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V)
Symbol
Parameter
Typ
Max
Units
Notes
CIO
Input/Output Capacitance
-
8
pF
1
CXTL
X1, X2 Crystal pin Capacitance
25
-
pF
1, 2
CCNT
Max. Allowable Capacitance on CNT (polled mode)
-
100
pF
Notes
1
This parameter is characterized but not tested.
2
The crystal attached to the X1/X2 pins must be rated as 12.5pF.
Data Retention (VDD = 2.7V to 3.6V)
Symbol
Parameter
Min
Units
Notes
TDR
Data Retention
@ +75°C
@ +80°C
@ +85°C
45
20
10
Years
AC Test Conditions
Input Pulse Levels
10% and 90% of VDD
Input Rise and Fall Times
5 ns
Input and Output Timing Levels
0.5 VDD
Output (SO) Load Capacitance
30 pF
Diagram Notes
All timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write
timing parameters apply to op-code, word address, and write data bits. Functional relationships are illustrated in the relevant data
sheet sections. These diagrams illustrate the timing parameters only.
Serial Data Bus Timing
CS
SCK
SI
SO
1/tCK
tCL
tCH
tCSH
tODV
tOH
tOD
tCSU
tSU
tH
tD
tR
tF
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