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参数资料
| 型号： | FM33256-G |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO14 |
| 封装： | GREEN, MS-012AB, SOIC-14 |
| 文件页数： | 27/28页 |
| 文件大小： | 320K |
| 代理商： | FM33256-G |
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FM33256/FM3316 SPI Companion w/ FRAM
Rev. 2.0
Feb. 2009
Page 8 of 28
Table 3. Alarm Match Bit Examples
Seconds
Minutes
Hours
Date
Months
Alarm condition
1
No match required = alarm 1/second
0
1
Alarm when seconds match = alarm 1/minute
0
1
Alarm when seconds, minutes match = alarm 1/hour
0
1
Alarm when seconds, minutes, hours match = alarm 1/date
0
1
Alarm when seconds, minutes, hours, date match = alarm 1/month
Real-time Clock Operation
The real-time clock (RTC) is a timekeeping device
that
can
be
capacitor-
or
battery-backed
for
permanently-powered operation. It offers a software
calibration feature that allows high accuracy.
The RTC consists of an oscillator, clock divider, and
a register system for user access. It divides down the
32.768 kHz time-base and provides a minimum
resolution of seconds (1Hz). Static registers provide
the user with read/write access to the time values. It
includes registers for seconds, minutes, hours, day-
of-the-week, date, months, and years. A block
diagram shown in Figure 9 illustrates the RTC
function.
The
user
registers
are
synchronized
with
the
timekeeper core using R and W bits in register 00h.
The R bit is used to read the time. Changing the R bit
from 0 to 1 transfers timekeeping information from
the core into the user registers 02-08h that can be
read by the user. If a timekeeper update is pending
when R is set, then the core will be updated prior to
loading the user registers. The user registers are
frozen and will not be updated again until the R bit is
cleared to a ‘0’.
The W bit is used to write new time/date values.
Setting the W bit to a ‘1’ stops the RTC and allows
the timekeeping core to be written with new data.
Clearing it to ‘0’ causes the RTC to start running
based on the new values loaded in the timekeeper
core. The RTC may be synchronized to another clock
source. On the 8
th clock of the write to register 00h
(W=0), the RTC starts counting with a timebase that
has been reset to zero milliseconds.
Note: Users should be certain not to load invalid
values, such as FFh, to the timekeeping registers.
Updates to the timekeeping core occur continuously
except when locked.
Figure 9. Real-time Clock Core Block Diagram
32.768 kHz
crystal
Oscillator
Clock
Divider
Update
Logic
512 Hz or
SW out
W
R
Seconds
7 bits
Minutes
7 bits
Hours
6 bits
Date
6 bits
Months
5 bits
Years
8 bits
CF
Days
3 bits
User Registers
1 Hz
/OSCEN
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相关代理商/技术参数 |
参数描述 |
|---|---|
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