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参数资料
| 型号： | FR3-8M |
| 厂商： | TechTools |
| 文件页数： | 21/38页 |
| 文件大小： | 0K |
| 描述： | EMULATOR FLASH FLEXROM III 8MEG |
| 标准包装： | 1 |
| 系列： | FlexROM™ III |
| 类型： | 存储器 |
| 适用于相关产品： | 外部 FLASH、EPROM 或 SRAM 设备 |
| 所含物品： | 需要 FR3 FlexROM III 仿真器、缆线（菊花链、LPT、迷你型夹和目标）、软件、有源缆线模块 |
| 其它名称： | FR38M |
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Cycle Interleaving
This technique depends on the emulator’s internal CYCLE time plus its target ACCESS time being less than
the target’s CYCLE time. Since Flex ROM III avoids interrupting target accesses, and uses hardware based
arbitration, it is possible to use CYCLE Interleaving if your target’s memory CYCLE time is greater than
300ns. Many micro-controllers and some microprocessors meet this criterion.
To use this method, configure Flex ROM II for READY mode arbitration, but leave the /READY line
disconnected.
Cycle Paralleling
This technique depends on you being able to find a signal in your target that guarantees the HOST exclusive
access to the emulator. This is often much easier than it sounds. For example, most processors cannot fetch
from their code space at the same time they are reading or writing their data space. In such systems, you
may be able to use the DATA WRITE line or the SRAM chip select signal to indicate to the emulator that it
is OK for the HOST to access the emulator’s memory. The idea is that as long as the target is busy writing
to its DATA space, it won’t attempt to access its code space and therefore could not collide with the HOST
access.
Other candidate signals might be IO READ, IO WRITE, or other peripheral chip selects. If your target
offers none of these, you might be able to create a valid signal. You could instrument your firmware to
periodically toggle an unused pin or access an unused but decoded memory or IO space to generate a
stimulus that allows the emulator to gain access.
To use this mode, configure the emulator for REQUEST/FEGRANT or REQUEST/REGRANT and attach
the selected signal to the emulator’s GRANT line. Do not connect the REQUEST line to anything. The
target is GRANTING us access every time it accesses the SRAM in this case.
The emulator will always wait for the START of a grant signal before initiating an access. The start is
defined by a FALLING edge or a RISING edge of the signal, depending on which arbitration mode you
selected (REGRANT or FEGRANT).
The time from the START of this GRANT signal to the next time the target may need data from the
emulator must be at least 300ns for this to work.
“SLAM IT”
This is not true arbitration, but is worth mentioning. In some cases, arbitration is not really required, as
long as the emulator does not tie up the bus too long. A good example of this is look-up data tables.
We have several customers using this technique to do on-the-fly modifications to Engine Controller ROMs,
wave-form synthesizer ROMs, graphics ROMs, character generator ROMs, etc.
If your application uses the EPROM or FLASH device to hold data rather than code, and it can tolerate an
occasional bad fetch (wrong data), it may be acceptable to simply allow Flex ROM III to collide with the
target during the access. Note that Flex ROM III will not hold the target’s bus or corrupt anything on the
target’s bus. It simply isolates itself from the target’s address and data bus during its access, causing the
target to fetch garbage during the collision. Each Flex ROM III access will isolate it from the target for
approximately 300ns.
You have two options when using this method. You can configure Flex ROM III for CYCLE Interleaving
(ready mode, but do not connect the ready line). This has the advantage of minimizing the probability of a
FlexROM III User’s Manual
19
Copyright ? 2001, TechTools
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