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参数资料
| 型号： | FS6377-01G-XTD |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 3-PLL PROGR 16-SOIC |
| 标准包装： | 48 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1115 (CN2011-ZH PDF) |
| 其它名称： | 766-1026 |
Rev. 4 | Page 24 of 24 | www.onsemi.com
FS6377
Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice
the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the
setting of the SEL_CD pin for as long as mux B is the PLL C output.
Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL
screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 7.
The register settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in
Figure 17. Individual bits can be poked, or the entire register value can be changed.
Figure 17: Register Screen
11.0 Revision History
Revision
Date
Modification
1
2004
Initial doc
2
2004
3
October 2007
Update content to new AMIS template
4
May 2008
Update to ON Semiconductor template
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