参数资料
| 型号： | FSAR001BNY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 35MA 8DIP |
| 标准包装： | 59 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 最高 600 V |
| 电压 - 压降（标准）： | 0.4V @ 35mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 35mA |
| 电流 - 限制（最小）： | 110mA |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
Functional Description
The FSAR001 is a compact, inductor-free, and highly
monolithic AC/DC linear converter housed in 8-lead DIP
packages and designed for non-isolated AC/DC
converter and home appliances. The FSAR001 provides
universal AC voltage input from 80V RMS to 265V RMS and
fixed-DC output voltage with current limiter for the non-
isolated AC/DC converter operating safety and stability.
The FSAR001 integrates many protection functions,
including output current limiter (I LIMIT ), output under-
voltage protection (UVP), over-temperature protector
(OTP), V DD over-voltage protection (OVP), and AC
synchronous signal detect function (V DET ).
As the FSAR001 operates in a typical application, the
startup current flows through the startup pin (V ST ) and
charges V DD capacitor. When the voltage of V DD is larger
than V TH_ON , the FSAR001 is turned on. After one AC
synchronous signal, the LDO is turned on and creates
output voltage (V OUT ). At steady state, the energy of V DD
capacitor decreases because of the chip operation and
load power dissipation. The behavior is shown in Figure
17 and the energy is recharged during conduction angle
interval (settled by R3 and R4) and under OVP function
limitation (V DD-OVPH ). With a view to increasing LDO
efficiency and system stability, FSAR001 sets the V DD
OVP voltage at 8.5V for 5V LDO regulator. The V DD
capacitor recovery angle controls below 50V RMS settled
by AC synchronous signal (DET sense voltage), detailed
in the following sections.
V IN
OUT Pin Under-Voltage Protection
When the output power is larger than the maximum
handling power of FSAR001, the condition causes the
output voltage to drop. Until the output voltage is less
than output nominal voltage -12% (5V – 0.625V =
4.375V), the UVP function disables the LDO stage and
waits until the next AC synchronous signal to restart the
FSAR001 automatically.
Current Limit
The FSAR001 includes a current limiter (ILIMIT) for safe
LDO operation. The limiter monitors the loading current
and directly controls the output delivery current of LDO.
The typical limited current set is 140mA to avoid the
output shorted to ground for an indefinite amount of time
without damaging the part. At over-current operation,
the I LIMIT function limits the maximum output current and
causes the unregulated output voltage to drop until the
UVP function occurs.
Over-Temperature Protection
The FSAR001 operates in highly converting ratio. The
thermal energy of FSAR001 is generated by the inner
converting power of the MOSFET. When the junction
temperature (T J ) exceeds 150°C, the OTP function
disables LDO stage and waits for the next AC
synchronous signal to restart. The over-temperature
hysteresis range is 40°C. After startup, the OTP function
monitors the junction temperature. When junction
Max
Max
Conduction angle
(set by R3&R4)
I IN
temperature decreases to the (T OTP-THYS ), the OTP
function enables the signal and allows LDO turn on. If
not, OTP function keeps the output function disabled
and continuously monitors the junction temperature. The
OTP function is designed to protect against abnormal
conditions and over-power operation.
DET Pin Selection
The DET pin connects to the commutated AC bus. It
sinks commutated AC voltage waveform used to provide
CV DD max
LDO
V OUT
Load
the AC synchronous signal and to set the V DD capacitor
recovery conduction angle. For synchronous signal
function, the AC synchronous signal used to enable
output voltage of the LDO and to trigger the output stage
V DD(capacitance)
Figure 17. Operating Principle
Startup Current
During FSAR001 startup, the startup current through the
rectifier and V ST pin charges the V DD capacitor with
maximum start current of V ST pin of 3.75mA and the
synchronous current controlled by R3 (1M ? ) and R4
(13k ? ), shown in Figure 1. The FSAR001 remains off
until the V DD voltage is larger than V TH-ON and the output
voltage is created at the same time. After the FSAR001
turns on, the V ST function is disabled by the control loop.
The major energy path changes from V ST pin from the
inner power MOSFET MV (V IN ).
? 2010 Fairchild Semiconductor Corporation
FSAR001 ? Rev. 1.0.1
8
protection with UVP and OTP. To limit the recovery-
conduction angle of the V DD capacitor, the DET pin
sense voltage (V DET ) is set between 0.14V ~0.95V.
During the sense-voltage range of the DET pin, the V DD
capacitor can be charged by the power MOSFET until
the OVP function is operating in every synchronous
cycle. As shown in Figure 18, the DET pin sense voltage
limits the charge time of t0~t1 and t2~ts/2 settled by R3
and R4. The maximum commutated input voltage of
FSAR001 can be determined by the following equation
with the maximum DET sense voltage defined:
www.fairchildsemi.com
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