参数资料
| 型号： | FSAR001BNY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 35MA 8DIP |
| 标准包装： | 59 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 最高 600 V |
| 电压 - 压降（标准）： | 0.4V @ 35mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 35mA |
| 电流 - 限制（最小）： | 110mA |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
Functional Description (Continued)
V DET , max ?
V DET , min ?
R 4
R 3 ? R 4
R 4
R 3 ? R 4
? V ac
? V ac
EQ 1
dissipation in the first stage. During the power MOSFET
turn-on, the current provided by the commutated AC
voltage is used to supply the loads and to charge the
V DD capacitor. In this way, when the power MOSFET
switches off, the loads receive the required currents by
the capacitor discharge. For this reason, it is important
to properly set the conduction angle.
V IN
V IN peak
For the V DD capacitor selection, during conduction angle
interval; the energy is drawn from commutated AC bus,
which not only provides the output requirement but also
I LOAD ? 10 m
C VDD ? , ( unit ? F ) EQ 2
V IN DET
t0
I IN
t1
t2
Ts/2
a.
Ts
t
recharges the V DD capacitor to OVP level. Outside of
conduction angle, the V DD capacitor supplies the whole
system requirement. The V DD capacitor can be reduced
by maximum loading power. The capacitor is evaluated
by Equation 2; the selection chart is shown in Figure 19.
1
b.
t
Figure 18.
Typical Waveforms
VDD Pin Over-Voltage Protection
After startup, FSAR001 turns on the OVP function.
During conduction angle interval, the V DD voltage has
two kinds of behavior. One is that if the V DD capacitor
recharges to OVP trigger point (8.5V for 5V version), the
FSAR001 turns off the power MOSFET to limit the
maximum V DD voltage. The other is that if the voltage of
V DD cannot recharge to the OVP level during the
conduction interval, the power MOSFET is turned off by
AC synchronous signal and continuously recharges V DD
capacitor at next duration. Using this technique, energy
is drawn from the AC mains only during the low-voltage
portions of each positive half cycle, reducing the
Figure 19.
V DD Capacitor vs. Output Current
? 2010 Fairchild Semiconductor Corporation
FSAR001 ? Rev. 1.0.1
9
www.fairchildsemi.com
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