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| 型号： | FSICEBASE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 71/84页 |
| 文件大小： | 0K |
| 描述： | BASE STATION FSICE FOR MCU MOD |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | * |
| 适用于相关产品： | * |
| 所含物品： | * |
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Using the Bus State Analyzer
Using the Bus State Analyzer
Sequential: A+B+C+D
After execution begins, the trace buffer begins storing data from the first cycle run. This
continues through the occurrence of event A, B, C, or D (whichever is enabled); data
storage ends after the specified number of post-trigger cycles.
Sequential: A+B -> C+D
After execution begins, the trace buffer begins storing data from the first cycle. This
continues through the occurrence of two events: A or B, followed by C or D. Data storage
ends after the specified number of post-trigger cycles.
If you select this mode, you must enable event A, event B, or both. You must enable event
C, event D, or both. Otherwise, the bus state analyzer cannot be triggered.
Sequential: A -> B -> C !D
After execution begins, the trace buffer begins storing data from all cycles. This continues
through the occurrence of three events, A, B, and C, in order, if event D does not occur. (If
D occurs, the sequencer starts again looking for event A.) Data storage ends after the
specified number of post-triggert cycles.
If you select this mode, you must enable events A, B, and C. Otherwise, the bus state
analyzer never can be triggered. If you disable event D, you convert this mode to a simple,
three-event sequence.
Sequential: A -> B -> C -> D
After execution begins, the trace buffer begins storing data from all cycles. This continues
through the occurrence of four events, A, B, C, and D, in order. Data storage ends after the
specified number of post trigger cycles.
If you select this mode, you must enable all four events A, B, C, then D. Otherwise, the
bus state analyzer cannot be triggered.
Sequential: Nth event: A+B+C+D
After execution begins, the trace buffer stores data until N occurrences of cycles that
match the definitions of events A, B, C, or D (whichever are enabled). Then the bus state
analyzer captures the next 1.33M/2 cycles. This puts the Nth captured occurrence of A, B,
C, or D in the middle of the trace buffer. The first half of the trace buffer will then contain
information before the Nth event and the other half will contain information after the Nth
event.
Note that the terminal count or post trigger cycles are valid only for counted or sequential
modes. For a counted mode, this field specifies the number of cycles to be stored. For a
Freescale In-Circuit Emulator Base User Manual, Rev. 1.1
Freescale Semiconductor
71
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FSICECBLBSA | 功能描述:仿真器/模拟器 BUS ANALYZER CABLE RoHS:否 制造商:Blackhawk 产品:System Trace Emulators 工具用于评估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| FSICECBLBSAE | 功能描述:仿真器/模拟器 BUS ANALYZER CABLE RoHS:否 制造商:Blackhawk 产品:System Trace Emulators 工具用于评估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| FSICEKITAP64 | 功能描述:仿真器/模拟器 FSICE EMULATOR KIT FOR 9 RoHS:否 制造商:Blackhawk 产品:System Trace Emulators 工具用于评估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| FSICEKITASAZ | 功能描述:仿真器/模拟器 FSICE EMUL FOR 908ASAZ RoHS:否 制造商:Blackhawk 产品:System Trace Emulators 工具用于评估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| FSICEKITEY | 功能描述:仿真器/模拟器 FSICE EMULATOR KIT FOR 9 RoHS:否 制造商:Blackhawk 产品:System Trace Emulators 工具用于评估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
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