参数资料
型号: FT232HQ-REEL
厂商: FTDI, Future Technology Devices International Ltd
文件页数: 21/65页
文件大小: 0K
描述: IC HS USB TO UART/FIFO 48QFN
应用说明: FT1248 Application Note
标准包装: 1
通道数: 1,UART
FIFO's: 4kb
规程: RS232,RS422,RS485
电源电压: 1.62 V ~ 1.98 V,2.97 V ~ 3.63 V
带并行端口:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(8x8)
包装: 标准包装
其它名称: 768-1102-6
Copyright 2012 Future Technology Devices International Limited
28
Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
Name
Min
Nom
Max
Units
Comments
t1
16.67
ns
CLKOUT period
t2
7.5
8.33
9.17
ns
CLKOUT high period
t3
7.5
8.33
9.17
ns
CLKOUT low period
t4
0
9
ns
CLKOUT to RXF#
t5
0
9
ns
CLKOUT to read DATA valid
t6
0
9
ns
OE# to read DATA valid
t7
7.5
16.67
ns
OE# setup time
t8
0
ns
OE# hold time
t9
7.5
16.67
ns
RD# setup time to CLKOUT (RD# low after OE# low)
t10
0
ns
RD# hold time
t11
0
9
ns
CLKOUT TO TXE#
t12
7.5
16.67
ns
Write DATA setup time
t13
0
ns
Write DATA hold time
t14
7.5
16.67
ns
WR# setup time to CLKOUT (WR# low after TXE# low)
t15
0
WR# hold time
Table 4.1 FT245 Synchronous FIFO Interface Signal Timings
This mode uses a synchronous interface to get high data transfer speeds. The chip drives a 60 MHz
CLKOUT clock for the external system to use.
Note that Asynchronous FIFO mode must be selected in the EEPROM before selecting the Synchronous
FIFO mode in software.
4.4.1 FT245 Synchronous FIFO Read Operation
A read operation is started when the chip drives RXF# low. The external system can then drive OE# low
to turn the data bus drivers around before acknowledging the data with the RD# signal going low. The
first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by
keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will
change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive
RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored.
4.4.2 FT245 Synchronous FIFO Write Operation
A write operation can be started when TXE# is low. WR# is brought low when the data is valid. A burst
operation can be done on every clock providing TXE# is still low. The external system must monitor TXE#
and its own WR# to check that data has been accepted. Both TXE# and WR# must be low for data to be
accepted.
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