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参数资料
| 型号： | GS81302T18E-350T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 8M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 1/36页 |
| 文件大小： | 1243K |
| 代理商： | GS81302T18E-350T |
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GS81302T08/09/18/36E-375/350/333/300/250
144Mb SigmaDDRTM-II
Burst of 2 SRAM
375 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.03 4/2011
1/36
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaDDR Interface
Common I/O bus
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write (x36 and x18) and Nybble Write (x8) function
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaDDR Family Overview
The GS81302T08/09/18/36E are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302T08/09/18/36E SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302T08/09/18/36E SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaDDR-II B2 RAMs always
transfer data in two packets. When a new address is loaded, A0
presets an internal 1 bit address counter. The counter
increments by 1 (toggles) for each beat of a burst of two data
transfer.
Common I/O x8 and x9 SigmaDDR-II B2 RAMs always
transfer data in two packets. When a new address is loaded,
the LSB is internally set to 0 for the first read or write transfer,
and incremented by 1 for the next transfer. Because the LSB
is tied off internally, the address field of a x8/x9 SigmaDDR-II
B4 RAM is always one address pin less than the advertised
index depth (e.g., the 16M x 8 has a 8M addressable index).
Parameter Synopsis
-375
-350
-333
-300
-250
tKHKH
2.66 ns
2.86 ns
3.0 ns
3.3 ns
4.0 ns
tKHQV
0.45 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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| GS8161EV32BD-200 | 512K X 32 CACHE SRAM, 6.5 ns, PBGA165 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS81302T36GE-333 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 144MBIT 4MX36 0.45NS 165FPBGA - Trays |
| GS81302T36GE-333I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 144MBIT 4MX36 0.45NS 165FPBGA - Trays |
| GS815018AB | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM |
| GS815018AB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2NS 119FPBGA - Trays |
| GS815018AB-250I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2NS 119FPBGA - Trays |
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