- 您现在的位置：买卖IC网 > PDF目录299161 > GS8322Z18E-225VT (GSI TECHNOLOGY) 2M X 18 ZBT SRAM, 7 ns, PBGA165 PDF资料下载
参数资料
| 型号： | GS8322Z18E-225VT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 2M X 18 ZBT SRAM, 7 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 8/39页 |
| 文件大小： | 1567K |
| 代理商： | GS8322Z18E-225VT |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页
GS8322Z18/36/72(B/E/C)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 12/2007
16/39
2002, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above table.
There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ and PE pins, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above tables.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
相关PDF资料 |
PDF描述 |
|---|---|
| GS8322ZV72GC-150IT | 512K X 72 ZBT SRAM, 8.5 ns, PBGA209 |
| GS8322ZV36GB-200T | 1M X 36 ZBT SRAM, 7.5 ns, PBGA119 |
| GS8322ZV36GE-225IT | 1M X 36 ZBT SRAM, 7 ns, PBGA165 |
| GS8324Z18B-166IT | 2M X 18 ZBT SRAM, 8.5 ns, PBGA119 |
| GS8324Z36B-150IT | 1M X 36 ZBT SRAM, 10 ns, PBGA119 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8322Z18E-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 36MBIT 2MX18 6.5NS/2.5NS 165FBGA - Trays |
| GS8322Z18E-250I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 36MBIT 2MX18 6.5NS/2.5NS 165FBGA - Trays |
| GS8322Z18E-250IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 36MBIT 2MX18 6.5NS/3NS 165FBGA - Trays |
| GS8322Z18E-250V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 36MBIT 2MX18 6.5NS/3NS 165FPBGA - Trays |
| GS8322Z18GB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 36MBIT 2MX18 7.5NS/3NS 119FBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。