- 您现在的位置：买卖IC网 > PDF目录299161 > GS8324Z36B-150IT (GSI TECHNOLOGY) 1M X 36 ZBT SRAM, 10 ns, PBGA119 PDF资料下载
参数资料
| 型号： | GS8324Z36B-150IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封装： | 14 X 22 MM, 1.27 MM PITCH, BGA-119 |
| 文件页数： | 1/46页 |
| 文件大小： | 1157K |
| 代理商： | GS8324Z36B-150IT |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页
Rev: 1.00 10/2001
1/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
2M x 18, 1M x 36, 512K x 72
36Mb Sync NBT SRAMs
250 MHz–133MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
FT pin for user-configurable flow through or pipeline operation
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 209-bump BGA package
Functional Description
Applications
The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.3
4.0
2.5
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
365
560
660
335
510
600
305
460
540
265
400
460
245
370
430
215
330
380
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
360
550
640
330
500
590
305
460
530
260
390
450
240
360
420
215
330
370
mA
Flow
Through
2-1-1-1
tKQ
tCycle
6.0
7.0
6.5
7.5
8.5
10
11
15
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
235
300
350
230
300
350
210
270
300
200
270
300
195
270
300
150
200
220
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
235
300
340
230
300
340
210
270
300
200
270
300
195
270
300
145
190
220
mA
相关PDF资料 |
PDF描述 |
|---|---|
| GS8324Z36GB-250IT | 1M X 36 ZBT SRAM, 6 ns, PBGA119 |
| GS8324Z72GC-133IT | 512K X 72 ZBT SRAM, 10 ns, PBGA209 |
| GS840E18GB-100T | 256K X 18 CACHE SRAM, 12 ns, PBGA119 |
| GS840E18GB-180 | 256K X 18 CACHE SRAM, 8 ns, PBGA119 |
| GS8641E18F-200IT | 4M X 18 CACHE SRAM, 7.5 ns, PBGA165 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS8324Z72C200 | 制造商:G.S.I. 功能描述: |
| GS8342D06BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-550 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
发布紧急采购，3分钟左右您将得到回复。