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参数资料
| 型号： | GS8324Z36B-150IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封装： | 14 X 22 MM, 1.27 MM PITCH, BGA-119 |
| 文件页数： | 31/46页 |
| 文件大小： | 1157K |
| 代理商： | GS8324Z36B-150IT |
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Rev: 1.00 10/2001
37/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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