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参数资料
型号： GS8641ZV18GE-200
厂商： GSI TECHNOLOGY
元件分类： SRAM
英文描述： 4M X 18 ZBT SRAM, 7.5 ns, PBGA165
封装： 17 X 15 MM, 1 MM PITCH, FBGA-165
文件页数： 1/30页
文件大小： 825K
代理商： GS8641ZV18GE-200
Product Preview
GS8641ZV18/32/36E-300/250/200/167
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–167 MHz
1.8 V VDD
1.8 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 9/2004
1/30
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V +10%/–10% core power supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with4Mb, 9Mb, 18Mb, and 36Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard 165-bump FP-BGA package
Functional Description
The GS8641ZV18/32/36E is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8641ZV18/32/36E may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8641ZV18/32/36E is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 165-bump FP-BGA package.
Parameter Synopsis
-300
-250
-200
-167
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.3
3.3
2.5
4.0
3.0
5.0
3.5
6.0
ns
Curr (x18)
Curr (x32/x36)
400
480
340
410
290
350
260
305
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5
6.5
7.5
8.0
ns
Curr (x18)
Curr (x32/x36)
285
330
245
280
220
250
210
240
mA
相关PDF资料
PDF描述
GS8644Z18GE-225T 4M X 18 ZBT SRAM, 6.5 ns, PBGA165
GS8662QT10BD-200I 8M X 9 QDR SRAM, 0.45 ns, PBGA165
GS8662QT10BGD-250T 8M X 9 QDR SRAM, 0.45 ns, PBGA165
GS8662T06BD-350I 8M X 8 DDR SRAM, 0.45 ns, PBGA165
GS8662T06BD-350T 8M X 8 DDR SRAM, 0.45 ns, PBGA165
相关代理商/技术参数
参数描述
GS864218B-167 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 8NS/3.5NS 119FBGA - Trays
GS864218B-167I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 8NS/3.5NS 119FBGA - Trays
GS864218B-167IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 72MBIT 4MX18 8NS/3.4NS 119FPBGA - Trays
GS864218B-167V 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 72MBIT 4MX18 8NS/3.4NS 119FPBGA - Trays
GS864218B-200 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 7.5NS/3NS 119FBGA - Trays
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