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参数资料
| 型号： | GS8644Z18GE-225T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 4M X 18 ZBT SRAM, 6.5 ns, PBGA165 |
| 封装： | 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件页数： | 1/31页 |
| 文件大小： | 1172K |
| 代理商： | GS8644Z18GE-225T |
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GS8644Z18E/GS8644Z36E
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
165-Pin BGA
Commercial Temp
Industrial Temp
Rev: 1.05b 5/2010
1/31
2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 9Mb, 18Mb, and 36Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 165-BGA package
RoHS-compliant 165-bump BGA package available
Functional Description
The GS8644Z18/36 is a 72Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8644Z18/36 may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8644Z18/36 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 165-bump BGA package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tKQ(x72)
tCycle
2.5
3.0
4.0
2.7
3.0
4.4
3.0
5.0
3.5
6.0
3.8
6.7
4.0
7.5
ns
Curr (x18)
Curr (x36)
Curr (x72)
385
450
540
360
415
505
335
385
460
305
345
405
295
325
385
265
295
345
mA
Flow
Through
2-1-1-1
tKQ
tCycle
6.5
7.0
7.5
8.5
ns
Curr (x18)
Curr (x36)
Curr (x72)
265
290
345
265
290
345
265
290
345
255
280
335
240
265
315
225
245
300
mA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8644Z36 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B-133 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B-133I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B-150 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
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