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参数资料
| 型号： | GS8644Z18GE-225T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 4M X 18 ZBT SRAM, 6.5 ns, PBGA165 |
| 封装： | 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件页数： | 11/31页 |
| 文件大小： | 1172K |
| 代理商： | GS8644Z18GE-225T |
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GS8644Z18E/GS8644Z36E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05b 5/2010
19/31
2003, GSI Technology
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKL
tKH
AB
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
W
Bn
A0–An
DQ
G
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8644Z36 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B-133 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B-133I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z36B-150 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
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