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参数资料
| 型号： | GS8662DT10BGD-400IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件页数： | 1/29页 |
| 文件大小： | 963K |
| 代理商： | GS8662DT10BGD-400IT |
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GS8662DT07/10/19/37BD-450/400/350/333/300
72Mb SigmaQuad-II+TM
Burst of 4 SRAM
450 MHz–300 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 5/2011
1/29
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
2.0 Clock Latency
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 4 Read and Write
Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid Pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad Family Overview
The GS8662DT07/10/19/37BD are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662DT07/10/19/37BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662DT07/10/19/37BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B4 RAMs always
transfer data in four packets, A0 and A1 are internally set to 0
for the first read or write transfer, and automatically
incremented by 1 for the next transfers. Because the LSBs are
tied off internally, the address field of a SigmaQuad-II+ B4
RAM is always two address pins less than the advertised index
depth (e.g., the 4M x 18 has a 1M addressable index).
Parameter Synopsis
-450
-400
-350
-333
-300
tKHKH
2.22 ns
2.5 ns
2.86 ns
3.0 ns
3.3 ns
tKHQV
0.45 ns
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
相关PDF资料 |
PDF描述 |
|---|---|
| GS8662Q18BD-357 | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BGD-357IT | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18GE-167IT | 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165 |
| GS8662R09BD-350 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662R09BGD-400I | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8662DT11BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT11BD-500I | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT11BD-550 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT11BD-550I | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT20BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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