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参数资料
| 型号： | GS8662DT10BGD-400IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件页数： | 26/29页 |
| 文件大小： | 963K |
| 代理商： | GS8662DT10BGD-400IT |
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Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
R
Synchronous Read
Input
Active Low
W
Synchronous Write
Input
Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
(x8 only)
K
Input Clock
Input
Active High
K
Input Clock
Input
Active Low
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
VREF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
Qn
Synchronous Data Outputs
Output
—
Dn
Synchronous Data Inputs
Input
—
Doff
Disable DLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
CQ
Output Echo Clock
Output
—
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
—
QVLD
Q Valid Output
Output
—
ODT
On-Die Termination
Input
Low = Low Impedance Range
High/Float = High Impedance Range
NC
No Connect
—
GS8662DT07/10/19/37BD-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
6/29
2011, GSI Technology
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
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