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参数资料
| 型号： | GS8662DT10BGD-400IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件页数： | 27/29页 |
| 文件大小： | 963K |
| 代理商： | GS8662DT10BGD-400IT |
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GS8662DT07/10/19/37BD-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
7/29
2011, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II+ SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II+ B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on
the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking
in a High on the Read Enable pin, R, begins a read port deselect cycle.
SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R High causes chip disable. A Low on
the Write Enable pin, W, and a High on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command
was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and
finally by the next rising edge of K.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Beat 3
0
Data In
Beat 4
1
0
Don’t Care
Data In
相关PDF资料 |
PDF描述 |
|---|---|
| GS8662Q18BD-357 | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BGD-357IT | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18GE-167IT | 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165 |
| GS8662R09BD-350 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662R09BGD-400I | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8662DT11BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT11BD-500I | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT11BD-550 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT11BD-550I | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662DT20BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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