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参数资料
| 型号： | GS88037BT-225I |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 256K X 36 CACHE SRAM, 2.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 1/19页 |
| 文件大小： | 425K |
| 代理商： | GS88037BT-225I |
Rev: 1.01 9/2003
1/19
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88037BT-333/300/275/250/225/200
256K x 36
9Mb Sync Burst SRAM
333 MHz–200 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
Single Cycle Deselect (SCD) operation
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS88037BT is a 9,437,184-bit (8,388,608-bit for x32
version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
SCD Pipelined Reads
The GS88037BT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88037BT operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
-333 -300 -275 -250 -225 -200 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.0
3.0
2.2
3.3
2.3
3.6
2.3
4.0
2.5
4.4
2.7
5.0
ns
3.3 V
Curr (x36)
435 395 360 330 300 270 mA
2.5 V
Curr (x36)
435 395 360 330 300 270 mA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS88037BT-250 | 制造商:GSI 制造商全称:GSI Technology 功能描述:256K x 36 9Mb Sync Burst SRAM |
| GS88037BT-250I | 制造商:GSI 制造商全称:GSI Technology 功能描述:256K x 36 9Mb Sync Burst SRAM |
| GS88037BT-250IV | 制造商:GSI 制造商全称:GSI Technology 功能描述:256K x 36 9Mb Sync Burst SRAM |
| GS88037BT-250V | 制造商:GSI 制造商全称:GSI Technology 功能描述:256K x 36 9Mb Sync Burst SRAM |
| GS88037BT-300 | 制造商:GSI 制造商全称:GSI Technology 功能描述:256K x 36 9Mb Sync Burst SRAM |
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