参数资料
| 型号： | HD3-6402R-9Z |
| 厂商： | Intersil |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC UART CMOS 5V 2MHZ 40-DIP |
| 标准包装： | 9 |
| 特点： | 低功率 CMOS |
| 通道数： | 8 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 带故障启动位检测功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-DIP |
| 包装： | 管件 |
3
Pin Description
PIN TYPE SYMBOL
DESCRIPTION
1VCC
Positive Voltage Supply
2
NC
No Connection
3
GND
Ground
4
I
RRD
A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.
5
O
RBR8
The contents of the RECEIVER BUFFER REGIS-
TER appear on these three-state outputs. Word for-
mats less than 8 characters are right justified to
RBR1.
6
O
RBR7
See Pin 5-RBR8
7
O
RBR6
See Pin 5-RBR8
8
O
RBR5
See Pin 5-RBR8
9
O
RBR4
See Pin 5-RBR8
10
O
RBR3
See Pin 5-RBR8
11
O
RBR2
See Pin 5-RBR8
12
O
RBR1
See Pin 5-RBR8
13
O
PE
A high level on PARITY ERROR indicates received
parity does not match parity programmed by control
bits. When parity is inhibited this output is low.
14
O
FE
A high level on FRAMING ERROR indicates the
first stop bit was invalid.
15
O
OE
A high level on OVERRUN ERROR indicates the
data received flag was not cleared before the last
character was transferred to the receiver buffer
register.
16
I
SFD
A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
17
I
RRC
The Receiver register clock is 16X the receiver
data rate.
18
I
DRR
A low level on DATA RECEIVED RESET clears
the data received output DR to a low level.
19
O
DR
A high level on DATA RECEIVED indicates a
character has been received and transferred to
the receiver buffer register.
20
I
RRI
Serial data on RECEIVER REGISTER INPUT is
clocked into the receiver register.
21
I
MR
A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiv-
er buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
VIH and tMR. Wait 18 clock cycles after the falling
edge of MR before beginning operation.
22
O
TBRE
A high level on TRANSMITTER BUFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has transferred its data to the transmitter register
and is ready for new data.
23
I
TBRL
A low level on TRANSMITTER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
high transition on TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
transmitted end to end.
24
O
TRE
A high level on TRANSMITTER REGISTER EMP-
TY indicates completed transmission of a charac-
ter including stop bits.
25
O
TRO
Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
26
I
TRB1
Character data is loaded into the TRANSMITTER
BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro-
grammed word length.
27
I
TBR2
See Pin 26-TBR1.
28
I
TBR3
See Pin 26-TBR1.
29
I
TBR4
See Pin 26-TBR1.
30
I
TBR5
See Pin 26-TBR1.
31
I
TBR6
See Pin 26-TBR1.
32
I
TBR7
See Pin 26-TBR1.
33
I
TBR8
See Pin 26-TBR1.
34
I
CRL
A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
35
I
PI
A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
36
I
SBS
A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
37
I
CLS2
These inputs program the CHARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)
38
I
CLS1
See Pin 37-CLS2.
39
I
EPE
When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A low
level selects odd parity.
40
I
TRC
The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
A 0.1
F decoupling capacitor from the VCC pin to the GND is
recommended.
PIN TYPE SYMBOL
DESCRIPTION
HD-6402
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