Rev. 7.00 Jan 31, 2006 page xv of xxvi
5.2.4
On-Chip Interrupts ............................................................................................... 71
5.2.5
Interrupt Exception Vectors and Priority Rankings ............................................. 71
5.3
Register Descriptions ........................................................................................................74
5.3.1
Interrupt Priority Registers A–E (IPRA–IPRE) ................................................... 74
5.3.2
Interrupt Control Register (ICR).......................................................................... 75
5.4
Interrupt Operation............................................................................................................ 76
5.4.1
Interrupt Sequence ............................................................................................... 76
5.4.2
Stack after Interrupt Exception Handling............................................................. 79
5.5
Interrupt Response Time ................................................................................................... 80
5.6
Usage Notes ...................................................................................................................... 81
Section 6 User Break Controller (UBC) ....................................................................... 83
6.1
Overview........................................................................................................................... 83
6.1.1
Features................................................................................................................ 83
6.1.2
Block Diagram ..................................................................................................... 84
6.1.3
Register Configuration......................................................................................... 85
6.2
Register Descriptions ........................................................................................................86
6.2.1
Break Address Registers (BAR) .......................................................................... 86
6.2.2
Break Address Mask Register (BAMR)............................................................... 87
6.2.3
Break Bus Cycle Register (BBR)......................................................................... 88
6.3
Operation........................................................................................................................... 90
6.3.1
Flow of User Break Operation ............................................................................. 90
6.3.2
Break on Instruction Fetch Cycles to On-Chip Memory...................................... 92
6.3.3
Program Counter (PC) Value Saved in User Break Interrupt Exception
Processing ............................................................................................................ 92
6.4
Setting User Break Conditions.......................................................................................... 93
6.5
Notes ................................................................................................................................. 94
6.5.1
On-Chip Memory Instruction Fetch..................................................................... 94
6.5.2
Instruction Fetch at Branches............................................................................... 94
6.5.3
Instruction Fetch Break........................................................................................95
Section 7 Clock Pulse Generator (CPG)....................................................................... 97
7.1
Overview........................................................................................................................... 97
7.2
Clock Source..................................................................................................................... 97
7.2.1
Connecting a Crystal Resonator........................................................................... 97
7.2.2
External Clock Input ............................................................................................ 99
7.3
Usage Notes ...................................................................................................................... 100
Section 8 Bus State Controller (BSC) ........................................................................... 103
8.1
Overview........................................................................................................................... 103