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参数资料
| 型号： | HD74CDC587 |
| 厂商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 锁相环时钟驱动器) |
| 中文描述： | 3.3 - V相位锁3环路时钟驱动器状态输出（3.3 V的锁相环时钟驱动器） |
| 文件页数： | 11/13页 |
| 文件大小： | 79K |
| 代理商： | HD74CDC587 |
HD74CDC587
11
Test Circuit
(SSTL_3)
C = 30 pF
25
Measurement
point
From output
V
TT
*1
25
Note:
1.
C
L
includes probe and jig capacitance.
Waveforms
phase error
t
V
OH
V
OL
1.1 V
1.9 V
1.5 V
1.5 V
0.8 V
2 V
2 V
0.8 V
1.5 V
TLH
t
THL
t
CLK
FBIN
(=FBOUT)
Notes:
1.
All input pulses are supplied by generators having the following characteristics: PRR
≤
150
MHz, Z
O
= 50
, tr = 0.7 ns, tf = 0.7 ns.
The outputs are measured one at a time with one transition per measurement.
V
TT
= V
REF
= 1.5 V
2.
3.
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