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参数资料
| 型号： | HD74CDC587 |
| 厂商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 锁相环时钟驱动器) |
| 中文描述： | 3.3 - V相位锁3环路时钟驱动器状态输出（3.3 V的锁相环时钟驱动器） |
| 文件页数： | 2/13页 |
| 文件大小： | 79K |
| 代理商： | HD74CDC587 |
HD74CDC587
2
required following changes to the SELn inputs, TEST inputs, or a change in frequency of the CLKIN
signal.
Features
Low output skew and jitter for clock distribution and synchronization
Internal loop filter eliminates the need for external RC network
Dedicated external feedback output and input for phase synchronization with the clock input
Applications for synchronous DRAM, high speed microprocessors, and SSTL_3
LVTTL-or SSTL_3-compatible inputs and outputs
Meets SSTL_3 class 1 and 2 specifications
Function Table
*1
(PLL enabled)
Inputs
*2
OE
Outputs
*3
F
IN
min
50 MHz
F
IN
max
150 MHz
FBOUT
1Y(0:3)
2Y(0:3)
3Y(0:3)
4Y(0:3)
H
1
×
1
×
Hi Z
Hi Z
Hi Z
Hi Z
L
H :
L :
Notes: 1. All SELn (n = 0, 1, 2, 3) inputs must be externally tied low for proper operation of the device.
2.
RESET
should be applied when the input and output frequencies change.
3. Thermal considerations may need to be observed; depending on V
CC
, temperature, number of
outputs loaded, and loading conditions.
50 MHz
150 MHz
1
×
1
×
1
×
1
×
High level
Low level
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