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参数资料
| 型号： | HD74CDC587 |
| 厂商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 锁相环时钟驱动器) |
| 中文描述： | 3.3 - V相位锁3环路时钟驱动器状态输出（3.3 V的锁相环时钟驱动器） |
| 文件页数： | 9/13页 |
| 文件大小： | 79K |
| 代理商： | HD74CDC587 |
HD74CDC587
9
Timing requirements
Item
Symbol Min
Max
Unit
Test Conditions
Input clock frequency
f
clock
50
150
MHz
Input clock duty cycle
40
60
%
Stabilization time
*1
—
5
ms
OE
(negative edge) or
RESET
(positive edge)
—
5
After power up and CLKIN
Note:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay and skew parameters given in the switching characteristics table are not
applicable.
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