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参数资料
| 型号： | HFA3860BIV96 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | nullDirect Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 文件页数： | 16/40页 |
| 文件大小： | 272K |
| 代理商： | HFA3860BIV96 |
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4-16
CCK Modulation
The spreading code length is 8 and based on
complementary codes. The chipping rate is 11 Mchip/s. The
symbol duration is exactly 8 complex chips long.
The following formula is used to derive the CCK code words
that shall be used for spreading both 5.5 and 11 Mbit/s:
(LSB to MSB), where c is the code word.
The terms:
1,
2,
3, and
4 are defined in clause below
for 5.5Mbps and 11Mbps.
This formula creates 8 complex chips (LSB to MSB) that are
transmitted LSB first.
This is a form of the generalized Hadamard transform
encoding where
1 is added to all code chips,
2 is added to
all odd code chips,
3 is added to all odd pairs of code chips
and
4 is added to all odd quads of code chips.
The phases
1 modify the phase of all code chips of the
sequence and are DQPSK encoded for 5.5 and 11Mbps.
This will take the form of rotating the whole symbol by the
appropriate amount relative to the phase of the preceding
symbol. Note that the MSB chip of the symbol defined above
is the chip that indicates the symbol’s phase and it is
transmitted last.
For the 5.5Mbps CCK mode, the output of the scrambler is
partitioned into nibbles. The first two bits are encoded as
differential modulation in accordance with Table 10. All odd
numbered symbols of the short Header or MPDU are given
an extra 180 degree (*) rotation in addition to the standard
DQPSK modulation as shown in the table. The symbols of
the MPDU shall be numbered starting with “0” for the first
symbol for the purposes of determining odd and even
symbols. That is, the MPDU starts on an even numbered
symbol.
The last data dibits d2, and d3 CCK encode the basic
symbol as specified in Table 11. This table is derived from
the formula above by setting
2 = (d2*pi)+ pi/2,
3 = 0, and
4 = d3*pi. In the table d2 and d3 are in the order shown and
the complex chips are shown LSB to MSB (left to right) with
LSB transmitted first.
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes
1 based on DQPSK. The
DQPSK encoder is specified in Table 10 above. The phase
change for
1 is relative to the phase
1 of the preceding
symbol. In the case of rate change, the phase change for
1
is relative to the phase
1 of the preceding CCK symbol. All
odd numbered symbols of the MPDU are given an extra 180
degree (*) rotation in accordance with the DQPSK
modulation as shown in Table 12. Symbol numbering starts
with “0” for the first symbol of the MPDU.
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode
2,
3,
and
4 respectively based on QPSK as specified in Table
12. Note that this table is binary, not Grey, coded.
TABLE 10. DQPSK ENCODING TABLE
DIBIT PATTERN (D(0), D(1))
D(0) IS FIRST IN TIME
EVEN SYMBOLS
PHASE CHANGE (+J
ω
)
ODD SYMBOLS
PHASE CHANGE (+J
ω
)
00
0
π
01
π
/2
π
3
π
/2 (-
π
/2)
11
0
10
3
π
/2 (-
π
/2)
π
/2
c
e
j
1
2
3
4
+
+
+
(
)
e
j
1
3
4
+
+
(
)
e
j
1
2
4
+
+
(
)
,
,
,
=
e
j
1
φ
4
+
(
)
e
j
1
2
3
+
+
(
)
e
j
1
3
+
(
)
e
j
1
2
+
(
)
e
j
1
,
–
,
,
,
–
TABLE 11. 5.5Mbps CCK ENCODING TABLE
d2, d3
00
:
1j
1
1j
-1
1j
1
-1j
1
01
:
-1j
-1
-1j
1
1j
1
-1j
1
10
:
-1j
1
-1j
-1
-1j
1
1j
1
11
:
1j
-1
1j
1
-1j
1
1j
1
TABLE 12. QPSK ENCODING TABLE
DIBIT PATTERN (D(I), D(I+1))
D(I) IS FIRST IN TIME
PHASE
00
0
01
π
/2
π
10
11
3
π
/2 (-
π
/2)
HFA3860B
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3861BIN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925IA | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA96 | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA50PA60C | RxxP2xx Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 15V; Power: 2W; EN 60950 certified, rated for 250VAC; UL-60950-1 / CSA C22.2 certified; 5.2kVDC Isolation for 1 Minute; Optional Continuous Short Circuit Protected; Wide Operating Temperature Range atfull 2 Watts Load, ?40??C to +85??C; Twin Chamber Transformer System; UL94V-0 Package Material; Efficiency to 80% |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860IV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
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