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参数资料
| 型号： | HFA3861AIN |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 288 MACROCELL 3.3 VOLT ISP CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封装： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件页数： | 34/37页 |
| 文件大小： | 440K |
| 代理商： | HFA3861AIN |
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34
TX_CLK to TX_PE Inactive (11Mbps)
t
PEH
0
65
ns (Notes 9, 20)
TX_RDY Inactive to Last Chip of MPDU Out
t
RI
-20
800
ns
TXD Modulation Extension
t
ME
2
-
μ
s (Notes 9, 13)
RX_PE Inactive Width
t
RLP
70
-
ns (Notes 9, 14)
RX_CLK Period (11Mbps Mode)
t
RCP
90
-
ns
RX_CLK Width Hi or Low (11Mbps Mode)
t
RCD
44
-
ns
RX_CLK to RXD
t
RDD
25
60
ns
MD_RDY to 1st RX_CLK
t
RD1
940
-
ns (Notes 9, 17)
RXD to 1st RX_CLK
t
RD1
940
-
ns
Setup RXD to RX_CLK
t
RDS
31
-
ns
RX_CLK to RX_PE Inactive (1Mbps)
t
REH
0
925
ns (Notes 9, 15)
RX_CLK to RX_PE Inactive (2Mbps)
t
REH
0
380
ns (Notes 9, 15)
RX_CLK to RX_PE Inactive (5.5Mbps)
t
REH
0
140
ns (Notes 9, 15)
RX_CLK to RX_PE Inactive (11Mbps)
t
REH
0
50
ns (Notes 9, 15)
RX_PE inactive to MD_RDY Inactive
t
RD2
5
30
ns (Note 16)
Last Chip of SFD in to MD_RDY Active
t
RD3
2.77
2.86
μ
s (Notes 9, 17)
RX Delay
2.77
2.86
μ
s (Notes 9, 18)
RESET Width Active
t
RPW
50
-
ns (Notes 9, 19)
RX_PE to CCA Valid
t
CCA
-
16
μ
s (Note 9)
RX_PE to RSSI Valid
t
CCA
-
16
μ
s (Note 9)
SCLK Clock Period
t
SCP
90
-
ns
SCLK Width Hi or Low
t
SCW
20
-
ns
Setup to SCLK + Edge (SD, SDI, R/W, CS)
t
SCS
30
-
ns
Hold Time from SCLK + Edge (SD, SDI, R/W, CS)
t
SCH
0
-
ns
SD Out Delay from SCLK + Edge
t
SCD
-
30
ns
SD Out Enable/Disable from R/W
t
SCED
-
15
ns (Note 9)
TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK
t
D2
-
40
ns
NOTES:
8. AC tests performed with C
L
= 40pF, I
OL
= 2mA, and I
OH
= -1mA. Input reference level all inputs V
CC
/2. Test V
IH
= V
CC
, V
IL
= 0V;
V
OH
= V
OL
= V
CC
/2.
9. Not tested, but characterized at initial design and at major process/design changes.
10. Measured from V
IL
to V
IH
.
11. I
OUT
/Q
OUT
are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits.
12. TX_PE must be inactive before going active to generate a new packet.
13. I
OUT
/Q
OUT
are modulated after last chip of valid data to provide ramp down time for RF/IF circuits.
14. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
15. RX_PE active to inactive delay to prevent next RX_CLK.
16. Assumes RX_PE inactive after last RX_CLK.
17. MD_RDY programmed to go active after SFD detect. (measured from I
IN
, Q
IN
).
18. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at I
IN
, Q
IN
to MD_RDY active.
19. Minimum time to insure Reset. RESET must be followed by an RX_PE pulse to insure proper operation. This pulse should not be used for first
receive or acquisition.
20. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within
40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns.
AC Electrical Specifications
V
CC
= 3.0V to 3.3V
±
10%, T
A
= -40
o
C to 85
o
C (Note 8)
(Continued)
PARAMETER
SYMBOL
MCLK = 44MHz
UNITS
MIN
MAX
HFA3861A
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相关代理商/技术参数 |
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|---|---|
| HFA3861AIN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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