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参数资料
| 型号： | HFA3861AIN |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 288 MACROCELL 3.3 VOLT ISP CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封装： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件页数： | 5/37页 |
| 文件大小： | 440K |
| 代理商： | HFA3861AIN |
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5
Control Port (4 Wire)
The serial control port is used to serially write and read
data to/from the device. This serial port can operate up to a
11MHz rate or 1/2 the maximum master clock rate of the
device, MCLK (whichever is lower). MCLK must be running
and RESET must be inactive during programming. This
port is used to program and to read all internal registers.
The first 8 bits always represent the address followed
immediately by the 8 data bits for that register. The LSB of
the address is a don’t care, but reserved for future
expansion. The serial transfers are accomplished through
the serial data pin (SD). SD is a bidirectional serial data
bus. Chip Select (CS), and Read/Write (R/W) are also
required as handshake signals for this port. The clock used
in conjunction with the address and data on SD is SCLK.
This clock is provided by the external source and it is an
input to the HFA3861A. The timing relationships of these
signals are illustrated in Figures 2 and 3. R/W is high when
data is to be read, and low when it is to be written. CS is an
asynchronous reset to the state machine. CS must be
active (low) during the entire data transfer cycle. CS
selects the serial control port device only. The serial control
port operates asynchronously from the TX and RX ports
and it can accomplish data transfers independent of the
activity at the other digital or analog ports.
The HFA3861A has 96 internal registers that can be
configured through the control port. These registers are
listed in the Configuration and Control Internal Register
table. Table 9 lists the configuration register number, a
brief name describing the register, the HEX address to
access each of the registers and typical values. The type
indicates whether the corresponding register is Read only
(R) or Read/Write (R/W). Some registers are two bytes
wide as indicated on the table (high and low bytes).
TXD
TXCLK
TX_RDY
RXD
RXC
MD_RDY
CS
SD
SCLK
R/W
SDI
RXI
RXQ
AGC
V
REF
I
REF
TX_PE
RX_PE
RESET
TEST
TX_PORT
RX_PORT
CONTROL_PORT
ANALOG
INPUTS
A/D
REFERENCE
POWER
DOWN
SIGNALS
TEST
PORT
8
HFA3861A
FIGURE 1. EXTERNAL INTERFACES
ANT_SEL
AGC
TXI
TXQ
ANALOG
OUTPUTS
NOTES:
1. The HFA3861A always uses the rising edge of SCLK to sample address and data and to generate read data.
2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data.
FIGURE 2. CONTROL PORT READ TIMING
FIGURE 3. CONTROL PORT WRITE TIMING
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCLK
SD
CS
R/W
LSB
DATA OUT
MSB
MSB
ADDRESS IN
FIRST ADDRESS BIT
FIRST DATABIT OUT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
SCLK
SD
CS
R/W
LSB
DATA IN
MSB
MSB
ADDRESS IN
HFA3861A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | Direct Sequence Spread Spectrum Baseband Processor(直接序列扩谱基带处理器) |
| HFA3983IV96 | 2.4GHz Power Amplifier and Detector |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3861AIN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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