- 您现在的位置：买卖IC网 > PDF目录385376 > HFA3861BIN (INTERSIL CORP) Direct Sequence Spread Spectrum Baseband Processor PDF资料下载
参数资料
| 型号： | HFA3861BIN |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封装： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件页数： | 8/36页 |
| 文件大小： | 733K |
| 代理商： | HFA3861BIN |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
8
Power Down Modes
The power consumption modes of the HFA3861B are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 61), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 62), which disables
the transmitter when inactive.
Reset (RESET, pin 63), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a
maximum of 10
μ
s before the device is operational.
The contents of the Configuration Registers are not effected
by any of the power down modes. No reconfiguration is
required when returning to operational modes. Activation of
RESET does corrupt learned values of AGC settings and
noise floor values. Optimum receiver operation may not be
achieved until these values are reestablished (typically
<50
μ
s of operation in noise only needed). The power
savings of activating RESET must be weighed against this.
Table 2 describes the power down modes available for the
HFA3861B (V
CC
= 3.3V). The table values assume that all
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
Transmitter Description
The HFA3861B transmitter is designed as a Direct
Sequence Spread Spectrum Phase Shift Keying (DSSS
PSK) modulator. It can handle data rates of up to 11Mbps
(refer to AC and DC specifications). The various modes of
the modulator are Differential Binary Phase Shift Keying
(DBPSK) for 1Mbps, Differential Quaternary Phase Shift
Keying (DQPSK) for 2Mbps, and Complementary Code
Keying (CCK) for 5.5Mbps and 11Mbps. These implement
data rates as shown in Table 3. The major functional blocks
of the transmitter include a network processor interface,
DPSK modulator, high rate modulator, a data scrambler and
a spreader, as shown in Figure 7. CCK is essentially a
quadra-phase form of M-ARY Orthogonal Keying. A
description of that modulation can be found in Chapter 5 of:
“Telecommunications System Engineering”, by Lindsey and
Simon, Prentis Hall publishing.
The preamble is always transmitted as the DBPSK
waveform while the header can be configured to be either
DBPSK, or DQPSK, and data packets can be configured for
DBPSK, DQPSK, or CCK. The preamble is used by the
receiver to achieve initial PN synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer
link. The transmitter generates the synchronization
preamble and header and knows when to make the DBPSK
to DQPSK or CCK switchover, as required.
TABLE 2. POWER DOWN MODES
MODE
RX_PE
TX_PE
RESET
AT
44MHz
DEVICE STATE
SLEEP
Inactive
Inactive
Active
1mA
Both transmit and receive functions disabled. Device in sleep mode. Control
Interface is still active. Register values are maintained. Device will return to its active
state within 10
μ
s.
STANDBY
Inactive
Inactive
Inactive
1.5mA
Both transmit and receive operations disabled. Device will resume its operational
state within 1
μ
s of RX_PE or TX_PE going active.
TX
Inactive
Active
Inactive
15mA
Receiver operations disabled. Receiver will return in its operational state within 1
of RX_PE going active.
μ
s
RX
Active
Inactive
Inactive
50mA
Transmitter operations disabled. Transmitter will return to its operational state within
2 MCLKs of TX_PE going active.
NO CLOCK
I
CC
Standby
Active
300
μ
A
All inputs at V
CC
or GND.
TABLE 3. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHz)
TX SETUP CR 5
BITS 1, 0
RX SIGNAL CR 63
BITS 7, 6
DATA RATE (Mbps)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
CCK
22
10
10
5.5
1.375
CCK
22
11
11
11
1.375
HFA3861B
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925IA | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA96 | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA50PA60C | RxxP2xx Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 15V; Power: 2W; EN 60950 certified, rated for 250VAC; UL-60950-1 / CSA C22.2 certified; 5.2kVDC Isolation for 1 Minute; Optional Continuous Short Circuit Protected; Wide Operating Temperature Range atfull 2 Watts Load, ?40??C to +85??C; Twin Chamber Transformer System; UL94V-0 Package Material; Efficiency to 80% |
| HFB50PA60C | Ultrafast, Soft Recovery Diode |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3861BIN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
发布紧急采购，3分钟左右您将得到回复。