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参数资料
| 型号： | HFA3863 |
| 厂商： | Intersil Corporation |
| 元件分类： | 基带处理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列扩谱基带处理器) |
| 中文描述： | 直接序列扩频基带处理器（直接序列扩谱基带处理器） |
| 文件页数： | 28/39页 |
| 文件大小： | 305K |
| 代理商： | HFA3863 |
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4-28
Bit 3
Enable test bus into RX and TX DAC (if below bit 2 is 0).
0 = normal.
1 = enable.
Bit 2
Enable RF A/D into RX DAC.
0 = normal.
1 = enable.
Bit 1
VRbit1.
Bit 0
VRbit0.
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 (Continued)
CONFIGURATION REGISTER 15 ADDRESS (1Eh) R/W AGC GAIN CLIP
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC gain clip (7-bit value, 0-127) this is the attenuator accumulator upper limit. The lower limit is 0.
CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC SATURATION COUNTS
Bits 7:4
AGC mid Saturation counts (0-15 range) these are the counts to kick in the low and mid attenuator steps (CR28).
Bits 3:0
AGC low Saturation Count (0-15 range).
CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC RF PAD VALUE
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
RXRF_AGC pad value to use in the RSSI calculation, Range 0 - 63dB (nominally 30dB).
CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC HI SAT
Bits 7:4
AGC high saturation attenuation value (0-30).
Note: hi saturation attenuation step actual value is programmed value times 2. This attenuation step will occur if the # of I and
Q sats is greater than hi saturation count.
Bits 3:0
AGC hi sat count (0-15 range).
CONFIGURATION REGISTER 19 ADDRESS (26h) R/W AGC LOCK IN LEVEL
Bits 7:5
CW detector scale multiplication factor. (xxxx.x). See CR35 and CR 49.
Set to 00h for forcing CW detect always active.
Set to 0Fh for forcing CW detector always inactive.
Bits 4:0
AGC Lock-in level (0-7.5 range). Note this is the inner lock window.
CONFIGURATION REGISTER 20 ADDRESS (28h) R/W AGC LOCK WINDOW POS.
Bits 7:5
AGC max lock count for antenna search. The number of updates required to lock AGC must be less than or equal to this count
for antenna diversity search to be allowed to run. Range 0 to 7.
Bit 4:0
AGC Lock Window positive side (0-15.5 range). Note: this is the outer lock window.
CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC BACKOFF
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5:0
AGC Backoff (xxxxx.x, 0-31.5 range) in half dB steps. This sets the operating headroom in the I and Q ADCs.
CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC LOOKUP TABLE ADDRESS
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5
AGC Look up table read control bit.
1 = Read AGC table at address given below.
0 = Read contents of CR23.
Bits 4:0
AGC lookup table address (32 address bits).
HFA3863
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3863IN | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3925IA1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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