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参数资料
| 型号： | HFA3863 |
| 厂商： | Intersil Corporation |
| 元件分类： | 基带处理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列扩谱基带处理器) |
| 中文描述： | 直接序列扩频基带处理器（直接序列扩谱基带处理器） |
| 文件页数： | 9/39页 |
| 文件大小： | 305K |
| 代理商： | HFA3863 |
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4-9
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps,
it uses two of those bits to select one of 4 complex spread
sequences from a table of CCK sequences and then QPSK
modulates that symbol with the remaining 2 bits. Thus, there
are 4 possible spread sequences to send at four possible
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase
reference for the data portion of the packet is the phase of
the last bit of the header. At 11Mbps, one byte is used as
above where 6 bits are used to select one of 64 spread
sequences for a symbol and the other 2 are used to QPSK
modulate that symbol. Thus, the total possible number of
combinations of sequence and carrier phases is 256. Of
these only one is sent.
The bit rate Table 3 shows examples of the bit rates and the
symbol rates and Figure 7 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3863 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions.
The HFA3863 generates its own preamble and header
information. It uses two packet preamble and header
configurations. The first is backwards compatible with the
existing IEEE 802.11-1997 1 and 2Mbps modes and the
second is the optional shortened mode which maximizes
throughput at the expense of compatibility with legacy
equipment.
TABLE 3. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHz)
TX SETUP CR 5
BITS 1, 0
RX SIGNAL CR 63
BITS 7, 6
DATA RATE
(Mbps)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
CCK
22
10
10
5.5
1.375
CCK
22
11
11
11
1.375
802.11 DSSS BPSK
1Mbps
BARKER
802.11 DSSS QPSK
2Mbps
BARKER
DATA
I
OUT
Q
OUT
CHIP
RATE
1 BIT ENCODED TO
ONE OF 2 CODE
WORDS
(TRUE-INVERSE)
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
SYMBOL
RATE
I vs. Q
11 MC/S
11 MC/S
1 MS/S
1 MS/S
11 CHIPS
11 CHIPS
FIGURE 7. MODULATION MODES
5.5Mbps CCK
COMPLEX
SPREAD FUNCTIONS
4 BITS ENCODED
TO ONE OF 16
COMPLEX CCK
CODE WORDS
11 MC/S
1.375 MS/S
8 CHIPS
11Mbps CCK
COMPLEX
SPREAD FUNCTIONS
8 BITS ENCODED
TO ONE OF 256
COMPLEX CCK
CODE WORDS
11 MC/S
1.375 MS/S
8 CHIPS
HFA3863
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3863IN | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3925IA1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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