参数资料
| 型号： | HI1-565AJD-5 |
| 厂商： | Intersil |
| 文件页数： | 9/9页 |
| 文件大小： | 0K |
| 描述： | CONV D/A 12BIT 6.7MHZ 24-DIP |
| 标准包装： | 165 |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 250mW |
| 工作温度： | 0°C ~ 75°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-CDIP（0.600"，15.24mm） |
| 供应商设备封装： | 24-DIP |
| 包装： | 管件 |
| 输出数目和类型： | 1 电流，单极；1 电流，双极 |
| 采样率（每秒）： | 6.7M |
9
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
HI-565A
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
bbb
C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
S
-D-
-A-
-C-
eA
-B-
aaa
CA - B
M
D
S
ccc
CA - B
M
D
S
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
S2
M
A
D24.6 MIL-STD-1835 CDIP2-T24 (D-3, CONFIGURATION C)
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.225
-
5.72
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.290
-
32.77
-
E
0.500
0.610
12.70
15.49
-
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.120
0.200
3.05
5.08
-
Q
0.015
0.075
0.38
1.91
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
N24
24
8
Rev. 0 4/94
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HI1-565AKD-5 | 制造商:Rochester Electronics LLC 功能描述:24 CDIP, 0+75, +15V,12-BIT D/A CONVERTER W/REF - Bulk 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
| HI1-565ASD/883 | 制造商:Intersil Corporation 功能描述:DAC SGL R-2R 12-BIT 24PIN SBDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:DAC 12BIT 6.7MHZ 0.25LSB 24CDIP /883 - Bulk |
| HI1-565ASD-2 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Speed, Monolithic D/A Converter with Reference |
| HI1-565ASD-8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI1-565ATD/883 | 制造商:Rochester Electronics LLC 功能描述:24 CDIP, -55+125,+15V,12-BIT D/A CONVERTER W/REF - Bulk 制造商:Harris Corporation 功能描述: |
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