参数资料
型号: HI5741-EVS
厂商: Intersil
文件页数: 2/13页
文件大小: 0K
描述: EVALUATION PLATFORM HI5741
标准包装: 1
DAC 的数量: 1
位数: 14
采样率(每秒): 100M
数据接口: 并联
设置时间: 20ns
DAC 型: 电流
工作温度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: HI5741
Application Note 9626
I15
V
GLITCH AREA = 1/2 (H x W)
BIT 13 (MSB)
BIT 12
I14
I13
HEIGHT (H)
BIT 11
BIT 10
I12
I11
WIDTH (W)
FIGURE 3. GLITCH AREA
t(ps)
4-BIT BINARY
I10
I9
I8
Since the glitch is a transient event, this leads designers to
believe that a simple low pass ?lter can be used to eliminate
or reduce the size of the glitch. In effect, low pass ?ltering a
glitch tends to “smear” the event and does little to remove
the energy of the transient.
TO
THERMOMETER
I7
Input Timing/Logic Levels
DECODER
I6
I5
I4
I3
I2
I1
SUMMING
JUNCTION (I OUT )
The HI5741 has a maximum clock rate speci?cation of
100MHz. The data setup time before the 50% point of the
rising edge of the clock is t S = 3ns (Min) and the hold time is
t H = 0.5ns (Min). Logic levels are 0.8V (Max) for an input low
and 2.0V (Min) for a logic high. The HI5741 is both TTL and
CMOS input compatible.
D11 - D0
CLK
FIGURE 2. THERMOMETER DECODER
t S
t H
FIGURE 4. HI5741 DATA TIMING
Designing to Minimize Glitch
One cause of Glitch is the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical, meaning that the turn off time is
faster than the turn on time. Unequal delay paths through the
device can cause one current source to change before
another. To minimize this, the Intersil HI5741 employes an
internal register just prior to the current sources which is
updated on the rising clock edge. In traditional DACs the
worst case glitch usually occurs at the major transition i.e.,
01 1111 1111 1111 to 10 0000 0000 0000. But in the HI5741
the worst case glitch is moved to the 00 0011 1111 1111 to
11 1100 000 0000 transition. This is achieved by the split
R/2R segmented current source architecture. This
decreases the amount of current switching at any one time
and reduces the glitch by a factor of 16.
Integral Linearity
The HI5741 has a full-scale range of 20.48mA. When driving
a 64 ? load the full scale voltage swing is 0V to -1V (the
internal 227 ? ladder resistance in parallel with the 64 ? load
results in an equivalent 50 ? load resistance). Most video
and communication applications use a 1V P-P voltage swing
which yields 20.48mA full scale current sink capability. With
a 1V P-P voltage swing on the HI5741 output an LSB is:
LSB = Full Scale Range/(2 N -1)
where N is the number of bits and the Full Scale Range is
1V P-P .
The LSB size for this application is 62.5 μ V. To determine the
Integral Linearity of the HI5741 the bit weights of each major
transition is taken. The Best Fit Straight Line method is used
to calculate the overall INL. Measurements are taken at bits
0 through 9 at each bit transition. Then all combinations of
the upper 4 bits are measured. Finally some worst case
codes are measured and the full scale is measured. Once
this is completed a best ?t straight line is drawn through the
data points and the worst case deviation is determined.
3-2
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