参数资料
| 型号： | HI5767/4CB-T |
| 厂商： | Intersil |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | CONV A/D 10BIT 40MSPS 28-SOIC |
| 标准包装： | 1,000 |
| 位数： | 10 |
| 采样率（每秒）： | 40M |
| 数据接口： | 并联 |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 310mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，双极 |
7
Maximum Output Current
-
0.2
mA
DIGITAL INPUTS
Input Logic High Voltage, VIH
CLK, DFS, OE
2.0
-
V
Input Logic Low Voltage, VIL
CLK, DFS, OE
-
0.8
V
Input Logic High Current, IIH
CLK, DFS, OE, VIH = 5V
-10.0
-
+10.0
A
Input Logic Low Current, IIL
CLK, DFS, OE, VIL = 0V
-10.0
-
+10.0
A
Input Capacitance, CIN
-
7
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 5V
4.0
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 5V
-
0.8
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 5V
-10
±1
10
A
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 3V
2.4
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 3V
-
0.5
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 3V
-10
±1
10
A
Output Capacitance, COUT
-
10
-
pF
TIMING CHARACTERISTICS
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Hold, tH
-
5
-
ns
Data Output Delay, tOD
-
6
-
ns
Data Output Enable Time, tEN
-
5
-
ns
Data Output Enable Time, tDIS
-
5
-
ns
Data Latency, tLAT
For a Valid Sample (Note 2)
-
7
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
20
Cycles
Sample Clock Pulse Width (Low)
fS = 40MSPS
11.3
12.5
-
ns
Sample Clock Pulse Width (High)
fS = 40MSPS
11.3
12.5
-
ns
Sample Clock Duty Cycle Variation
fS = 40MSPS
-
±5
-
%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
4.75
5.0
5.25
V
Digital Supply Voltage, DVCC1
4.75
5.0
5.25
V
Digital Output Supply Voltage, DVCC2
At 3.0V
2.7
3.0
3.3
V
At 5.0V
4.75
5.0
5.25
V
Supply Current, ICC
fIN = 1MHz and DFS = “0”
-
62
-
mA
Power Dissipation
fIN = 1MHz and DFS = “0”
-
310
-
mW
Offset Error Sensitivity,
VOS
AVCC or DVCC = 5V ±5%
-
±0.7
-
LSB
Gain Error Sensitivity,
FSE
AVCC or DVCC = 5V ±5%
-
±0.1
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25
oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5767
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