参数资料
型号: HI7190IP
厂商: Intersil
文件页数: 11/25页
文件大小: 0K
描述: IC ADC 24BIT PROGBL SER 20-PDIP
标准包装: 18
位数: 24
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 32.5mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 20-DIP(0.300",7.62mm)
供应商设备封装: 20-PDIP
包装: 管件
输入数目和类型: 1 个差分,单极;1 个差分,双极
19
FN3612.10
June 27, 2006
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read cycle,
during the instruction phase of the communication cycle, the
Instruction Byte should be set to a read transfer (R/W = 0).
When reading the serial port, data is driven out of the HI7190
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Detailed Register Descriptions
Data Output Register
The Data Output Register contains 24 bits of converted data.
This register is a read only register.
BYTE 2
MSB
22212019181716
D23
D22
D21
D20
D19
D18
D17
D16
BYTE 1
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
BYTE 0
7654321
LSB
D7
D6
D5
D4
D3
D2
D1
D0
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE WRITE
CS
SCLK
SDIO
SDO
THREE-STATE
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13 B14 B15
FIGURE 14. DATA WRITE CYCLE, SCLK IDLE LOW
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE WRITE
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13 B14
B15
THREE-STATE
FIGURE 15. DATA WRITE CYCLE, SCLK IDLE HIGH
DATA TRANSFER PHASE - TWO-BYTE READ
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13 B14
B15
IR WRITE PHASE
FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW
HI7190
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