参数资料
| 型号： | HI7190IP |
| 厂商： | Intersil |
| 文件页数： | 7/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-PDIP |
| 标准包装： | 18 |
| 位数： | 24 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 20-PDIP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
15
FN3612.10
June 27, 2006
System Offset/Internal Gain Calibration Mode
Please note: System Offset/Internal Gain is only valid when
operating in a gain of one. In addition, the offset and gain errors
are not reduced as with the full system calibration.
The System Offset/Internal Gain Calibration Mode is a single
step process that updates the Offset Calibration Register,
the Positive Full Scale Calibration Register, and the
Negative Full Scale Calibration Register. First the external
differential signal applied to the VIN inputs is converted and
that value is stored in the Offset Calibration Register. The
user must apply the zero point or offset voltage to the
HI7190 analog inputs and allow the signal to settle before
selecting this mode.
After this is completed the Positive and Negative Full Scale
Calibration Registers are updated. The inputs VINHI and VINLO
are disconnected and the external reference is switched in. The
HI7190 then takes 3 conversion cycles to sample the data and
update the Positive Full Scale Calibration Register. Next the
polarity of the reference voltage across the VINHI and VINLO
terminals is reversed and after 3 conversion cycles the
Negative Full Calibration Register is updated. The values
stored in the Positive and Negative Full Scale Calibration
Registers correct for any internal gain errors in the A/D transfer
function. After 3 more conversion cycles, the DRDY line will
activate signaling that the calibration is complete and valid data
is present in the Data Output Register.
System Gain Calibration Mode
The Gain Calibration Mode is a single step process that
updates the Positive and Negative Full Scale Calibration
Registers. This mode will convert the external differential
signal applied to the VIN inputs and then store that value in
the Negative Full Scale Calibration Register. Then the
polarity of the input is reversed internally and another
conversion is performed. This conversion result is written to
the Positive Full Scale Calibration Register. The user must
apply the +Full Scale voltage to the HI7190 analog inputs
and allow the signal to settle before selecting this mode.
After 1 more conversion period the DRDY line will activate
signaling the calibration is complete and valid data is present
in the data output register.
Reserved
This mode is not used in the HI7190 and should not be
selected. There is no internal detection logic to keep this
condition from being selected and care should be taken not
to assert this bit combination.
Offset and Span Limits
There are limits to the amount of offset and gain which can
be adjusted out for the HI7190. For both bipolar and unipolar
modes the minimum and maximum input spans are
0.2 x VREF/GAIN and 1.2 x VREF/GAIN respectively.
In the unipolar mode the offset plus the span cannot exceed
the 1.2 x VREF /GAIN limit. So, if the span is at its minimum
value of 0.2 x VREF/GAIN, the offset must be less than 1 x
VREF /GAIN. In bipolar mode the span is equidistant around
the voltage used for the zero scale point. For this mode the
offset plus half the span cannot exceed 1.2 x VREF/GAIN. If
the span is at
±0.2 x VREF /GAIN, then the offset can not be
greater than
±2 x VREF /GAIN.
Serial Interface
The HI7190 has a flexible, synchronous serial communication
port to allow easy interfacing to many industry standard
microcontrollers and microprocessors. The serial I/O is
compatible with most synchronous transfer formats, including
both the Motorola 6805/11 SPI and Intel 8051 SSR protocols.
The Serial Interface is a flexible 2-wire or 3-wire hardware
interface where the HI7190 can be configured to read and
write on a single bidirectional line (SDIO) or configured for
writing on SDIO and reading on the SDO line.
The interface is byte organized with each register byte
having a specific address and single or multiple byte
transfers are supported. In addition, the interface allows
flexibility as to the byte and bit access order. That is, the user
can specify MSB/LSB first bit positioning and can access
bytes in ascending/descending order from any byte position.
The serial interface allows the user to communicate with 5
registers that control the operation of the device.
Data Output Register - a 24-bit, read only register
containing the conversion results.
Control Register - a 24-bit, read/write register containing
the setup and operating modes of the device.
Offset Calibration Register - a 24-bit, read/write register
used for calibrating the zero point of the converter or system.
Positive Full Scale Calibration Register - a 24-bit,
read/write register used for calibrating the Positive Full Scale
point of the converter or system.
Negative Full Scale Calibration Register - a 24-bit,
read/write register used for calibrating the Negative Full
Scale point of the converter or system.
Two clock modes are supported. The HI7190 can accept the
serial interface clock (SCLK) as an input from the system or
generate the SCLK signal as an output. If the MODE pin is
logic low the HI7190 is in external clocking mode and the
SCLK pin is configured as an input. In this mode the user
supplies the serial interface clock and all interface timing
specifications are synchronous to this input. If the MODE pin
is logic high the HI7190 is in self-clocking mode and the
SCLK pin is configured as an output. In self-clocking mode,
SCLK runs at FSCLK = OSC1/8 and stalls high at byte
boundaries. SCLK does NOT have the capability to stall low
in this mode. All interface timing specifications are
synchronous to the SCLK output.
Normal operation in self-clocking mode is as follows (See
HI7190
相关PDF资料 |
PDF描述 |
|---|---|
| HI7191IP | IC ADC 24BIT PROGBL SER 20-PDIP |
| HI9P5701K-5 | CONV A/D 6BIT 30MSPS 18-SOIC |
| HMC700LP4E | IC FRACT-N PLL 16BIT 24QFN |
| HMC703LP4E | IC FRACT-N PLL W/SWEEPR 24QFN |
| HMC704LP4E | IC FRACT-N PLL 16BIT 24QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HI7190IPZ | 功能描述:模数转换器 - ADC W/ANNEAL ADC 24BIT 1 0HZ SIGMADELTA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| HI7191 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191IB | 功能描述:IC ADC 24BIT PROGBL SER 20-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| HI7191IBZ | 功能描述:模数转换器 - ADC ADC 24BIT SIGMADELTA 20 IND RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
发布紧急采购，3分钟左右您将得到回复。