参数资料
| 型号： | HI7191IBZ-T |
| 厂商： | Intersil |
| 文件页数： | 25/25页 |
| 文件大小： | 0K |
| 描述： | CONV A/D 24BIT SIGMA/DLTA 20SOIC |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 位数： | 24 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 其它名称： | HI7191IBZ-TDKR |
9
FN4138.8
June 1, 2006
Definitions
Integral Non-Linearity, INL, is the maximum deviation of
any digital code from a straight line passing through the
endpoints of the transfer function. The endpoints of the
transfer function are zero scale (a point 0.5 LSB below the
first code transition 000...000 and 000...001) and full scale (a
point 0.5 LSB above the last code transition 111...110 to
111...111).
Differential Non-Linearity, DNL, is the deviation from the
actual difference between midpoints and the ideal difference
between midpoints (1 LSB) for adjacent codes. If this
difference is equal to or more negative than 1 LSB, a code
will be missed.
Offset Error, VOS, is the deviation of the first code transition
from the ideal input voltage (VIN - 0.5 LSB). This error can
be calibrated to the order of the noise level shown in Table 1.
Full Scale Error, FSE, is the deviation of the last code
transition from the ideal input full scale voltage
(VIN-+VREF/Gain - 1.5 LSB). This error can be calibrated
to the order of the noise level shown in Table 1.
Input Span, defines the minimum and maximum input
voltages the device can handle while still calibrating properly
for gain.
Noise, eN, Table 1 shows the peak-to-peak and RMS noise
for typical notch and -3dB frequencies. The device
programming was for bipolar input with a VREF of +2.5V. This
implies the input range is 5V. The analysis was performed on
100 conversions with the peak-to-peak output noise being
the difference between the maximum and minimum readings
over a rolling 10 conversion window. The equation to convert
the peak-to-peak noise data to ENOB is:
ENOB = Log2 (VFS/VNRMS)
where: VFS = 5V, VNRMS = VNP-P/CF and
CF = 6.6 (Imperical Crest Factor)
The noise from the part comes from two sources, the
quantization noise from the analog-to-digital conversion
process and device noise. Device noise (or Wideband
Noise) is independent of gain and essentially flat across the
frequency spectrum. Quantization noise is ratiometric to
input full scale (and hence gain) and its frequency response
is shaped by the modulator.
Looking at Table 1, as the cutoff frequency increases the
output noise increases. This is due to more of the
quantization noise of the part coming through to the output
and, hence, the output noise increases with increasing
-3dB frequencies. For the lower notch settings, the output
noise is dominated by the device noise and, hence, altering
the gain has little effect on the output noise. At higher notch
frequencies, the quantization noise dominates the output
noise and, in this case, the output noise tends to decrease
with increasing gain.
Since the output noise comes from two sources, the effective
resolution of the device (i.e., the ratio of the input full scale to
the output RMS noise) does not remain constant with
increasing gain or with increasing bandwidth. It is possible to
do post-filtering (such as brick wall filtering) on the data to
improve the overall resolution for a given -3dB frequency
and also to further reduce the output noise.
Circuit Description
The HI7191 is a monolithic, sigma delta A/D converter which
operates from
±5V supplies and is intended for
measurement of wide dynamic range, low frequency signals.
It contains a Programmable Gain Instrumentation Amplifier
(PGIA), sigma delta ADC, digital filter, bidirectional serial port
(compatible with many industry standard protocols), clock
oscillator, and an on-chip controller.
The signal and reference inputs are fully differential for
maximum flexibility and performance. Normally VRHI and
VRLO are tied to +2.5V and AGND respectively. This allows
for input ranges of 2.5V and 5V when operating in the
unipolar and bipolar modes respectively (assuming the PGIA
is configured for a gain of 1). The internal PGIA provides
input gains from 1 to 128 and eliminates the need for
external pre-amplifiers. This means the device will convert
signals ranging from 0V to +20mV and 0V to +2.5V when
operating in the unipolar mode or signals in the range of
±20mV to ±2.5V when operating in the bipolar mode.
The input signal is continuously sampled at the input to the
HI7191 at a clock rate set by the oscillator frequency and the
selected gain. This signal then passes through the sigma
delta modulator (which includes the PGIA) and emerges as a
pulse train whose code density contains the analog signal
information. The output of the modulator is fed into the sinc3
digital low pass filter. The filter output passes into the
calibration block where offset and gain errors are removed.
The calibrated data is then coded (2’s complement, offset
binary or binary) before being stored in the Data Output
Register. The Data Output Register update rate is
determined by the first notch frequency of the digital filter.
This first notch frequency is programmed into HI7191 via the
Control Register and has a range of 10Hz to 1.953kHz which
corresponds to -3dB frequencies of 2.62Hz and 512Hz
respectively.
Output data coding on the HI7191 is programmable via the
Control Register. When operating in bipolar mode, data
output can be either 2’s complement or offset binary. In
unipolar mode output is binary.
The DRDY signal is used to alert the user that new output
data is available. Converted data is read via the HI7191
serial I/O port which is compatible with most synchronous
HI7191
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