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| 型号： | HIP4020IBZ |
| 厂商： | Intersil |
| 文件页数： | 6/9页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER FULL-BRIDGE 20-SOIC |
| 标准包装： | 38 |
| 配置： | 半桥 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 2.5µs |
| 电流 - 峰： | 625mA |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 3 V ~ 12 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
| 产品目录页面： | 1239 (CN2011-ZH PDF) |
HIP4020
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor
terminal OUTA) at the moment of Dynamic Braking will
continue to flow through Q2 to the V SSA and V SSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
V SS ground reference terminal. However, the maximum
supply level from V DD to V SSA or V SSB must not be greater
than the Absolute Maximum Supply Voltage rating.
Terminals A1, B1, A2, B2, ENA and ENB are internally
connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level
Converters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV.
However, these devices are sensitive to electrostatic
discharge. Proper I.C. handling procedures should be
followed.
V DD
Q4 to the V SSB and V SSA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where V DD to V SS are the Power Supply reference
terminals for the Control Logic, the lowest practical supply
INPUT
LEVEL
CONV.
voltage for proper logic control should be no less than 2.0V.
The V SSA and V SSB terminals are separate and
independent from V SS and may be more negative than the
A1
(DIR)
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
V DD
P-DR
LIMIT
A2
(BRAKE)
OT AND OC
PROTECT
Q1
Q2
D1
D2
OUTA
ENA
(ENABLE)
B1
(DIR)
N-DR
LIMIT
P-DR
LIMIT
V SSA
V DD
B2
(BRAKE)
OT AND OC
PROTECT
Q3
Q4
D3
D4
OUTB
ENB
N-DR
LIMIT
(ENABLE)
V SSB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
6
FN3976.3
December 20, 2005
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