参数资料
| 型号： | HIP6004BCVZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM VOLTAGE MON 20TSSOP |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel Pentium?，II，Pro |
| 输入电压： | 5V，12V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
HIP6004B
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES
MILLIMETERS
INDEX
AREA
H
0.25(0.010) M
B M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
E
-B-
A
A1
0.0926
0.0040
0.1043
0.0118
2.35
0.10
2.65
0.30
-
-
1
2
3
L
B
C
0.014
0.0091
0.019
0.0125
0.35
0.23
0.49
0.32
9
-
SEATING PLANE
D
0.4961
0.5118
12.60
13.00
3
-A-
D
A
h x 45 o
E
0.2914
0.2992
7.40
7.60
4
e
0.050 BSC
1.27 BSC
-
e
-C-
A1
μ α
C
H
h
L
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
5
6
B
0.10(0.004)
N
20
20
7
0.25(0.010) M
C A M
B S
α
0 o
8 o
0 o
8 o
-
Rev. 1 1/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
13
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