参数资料
| 型号： | HIP6004BCVZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/15页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM VOLTAGE MON 20TSSOP |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel Pentium?，II，Pro |
| 输入电压： | 5V，12V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
HIP6004B
I PEAK = -----------------------------------------------------
Over-Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r DS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
4V
2V
0V
15A
10A
5A
0A
TIME (20ms/DIV)
FIGURE 4. OVER-CURRENT OPERATION
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R OCSET )
programs the over-current trip level. An internal 200μA current
sink develops a voltage across R OCSET that is referenced to
V IN . When the voltage across the upper MOSFET (also
referenced to V IN ) exceeds the voltage across R OCSET , the
over-current function initiates a soft-start sequence. The soft-
start function discharges C SS with a 10μA current sink and
inhibits PWM operation. The soft-start function recharges
C SS , and PWM operation resumes with the error amplifier
clamped to the SS voltage. Should an overload occur while
recharging C SS , the soft start function inhibits PWM operation
while fully charging C SS to 4V to complete its cycle. Figure 4
shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C SS
charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.
The over-current function will trip at a peak inductor current
(I PEAK) determined by:
I OCSET x R OCSET
r DS ( ON )
where I OCSET is the internal OCSET current source (200 μ A
typical). The OC trip point varies mainly due to the
MOSFET’s r DS(ON) variations. To avoid over-current
tripping in the normal operating load range, find the R OCSET
resistor from the equation above with:
1. The maximum r DS(ON) at the highest junction
temperature.
2. The minimum I OCSET from the specification table.
3. Determine I PEAK for I PEAK > I OUT ( MAX ) + ( ? I ) ? 2 ,
where ? I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R OCSET to smooth the voltage across R OCSET in the
presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a HIP6004B converter is programmed
to discrete levels between 1.8V DC and 3.5V DC . The voltage
identification (VID) pins program an internal voltage reference
(DACOUT) with a TTL-compatible 5-bit digital-to-analog
converter (DAC). The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage
for the 32 different combinations of connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exercise
the overvoltage protection.
‘11111’ VID pin combination resulting in a 0V output setting
activates the Power-On Reset function and disables the gate
drives circuitry. For this specific VID combination, though,
PGOOD asserts a high level. This unusual behavior has been
implemented in order to allow for operation in dual-
microprocessor systems where AND-ing of the PGOOD signals
from two individual power converters is implemented.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
7
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